From: Luke Kenneth Casson Leighton Date: Mon, 27 Jan 2020 15:54:26 +0000 (+0000) Subject: add comments, remove one of the Muxes X-Git-Tag: ls180-24jan2020~327 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=33cd66fb4eb9aab7a181a6423eb4fa45153c138d;p=ieee754fpu.git add comments, remove one of the Muxes --- diff --git a/src/ieee754/fsgnj/fsgnj.py b/src/ieee754/fsgnj/fsgnj.py index dbdb23d1..d6de4d4b 100644 --- a/src/ieee754/fsgnj/fsgnj.py +++ b/src/ieee754/fsgnj/fsgnj.py @@ -32,9 +32,10 @@ class FSGNJPipeMod(PipeModBase): def elaborate(self, platform): m = Module() - width = self.pspec.width + # useful clarity variables comb = m.d.comb - + width = self.pspec.width + opcode = self.i.ctx.op z1 = self.o.z # Decode the input operands into sign, exponent, and mantissa @@ -45,14 +46,13 @@ class FSGNJPipeMod(PipeModBase): comb += [a1.v.eq(self.i.a), b1.v.eq(self.i.b)] - opcode = self.i.ctx.op - - - # Calculate the sign bit - sign = Signal(reset_less=True) + # Calculate the sign bit, with a chain of muxes. has to be done + # this way due to (planned) use of PartitionedSignal. decreases + # readability slightly, but hey. # Handle opcodes 0b00 and 0b01, copying or inverting the sign bit of B - sign = Mux(opcode[0], ~b1.s, b1.s) + sign = opcode[0] ^ b1.s # op[0]=0, sign unmodified, op[0]=1 inverts. + # Handle opcodes 0b10 and 0b11, XORing sign bits of a and b together. # opcode 0b11 is not defined in the RISCV spec; it is handled # here as equivalent to opcode 0b10 (i.e. a1.s XOR b1.s) @@ -60,7 +60,6 @@ class FSGNJPipeMod(PipeModBase): # same as opcode 0b00 (1 less Mux). sign = Mux(opcode[1], b1.s ^ a1.s, sign) - # Create the floating point number from the sign bit # calculated earlier and the exponent and mantissa of operand a comb += z1.eq(a1.fp.create2(sign, a1.e, a1.m))