From: Nils Asmussen Date: Fri, 14 Feb 2020 14:39:44 +0000 (+0100) Subject: arch-riscv: fault according to status.{TVM,TSK,TW}. X-Git-Tag: v20.0.0.0~114 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=33d651b254271e44e6bc0a557ed3f9177cf27ea8;p=gem5.git arch-riscv: fault according to status.{TVM,TSK,TW}. Change-Id: I38dddadb3373d2156b8fc57eabff861a062021cf Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25654 Tested-by: kokoro Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power --- diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa index 870615582..8dad14caa 100644 --- a/src/arch/riscv/isa/decoder.isa +++ b/src/arch/riscv/isa/decoder.isa @@ -1779,13 +1779,16 @@ decode QUADRANT default Unknown::unknown() { } 0x8: decode RS2 { 0x2: sret({{ - if (xc->readMiscReg(MISCREG_PRV) == PRV_U) { + STATUS status = xc->readMiscReg(MISCREG_STATUS); + auto pm = (PrivilegeMode)xc->readMiscReg( + MISCREG_PRV); + if (pm == PRV_U || + (pm == PRV_S && status.tsr == 1)) { fault = make_shared( - "sret in user mode", machInst); + "sret in user mode or TSR enabled", + machInst); NPC = NPC; } else { - STATUS status = xc->readMiscReg( - MISCREG_STATUS); xc->setMiscReg(MISCREG_PRV, status.spp); status.sie = status.spie; status.spie = 1; @@ -1795,10 +1798,26 @@ decode QUADRANT default Unknown::unknown() { } }}, IsReturn); 0x5: wfi({{ + STATUS status = xc->readMiscReg(MISCREG_STATUS); + auto pm = (PrivilegeMode)xc->readMiscReg( + MISCREG_PRV); + if (pm == PRV_U || + (pm == PRV_S && status.tw == 1)) { + fault = make_shared( + "wfi in user mode or TW enabled", + machInst); + } // don't do anything for now }}, No_OpClass); } 0x9: sfence_vma({{ + STATUS status = xc->readMiscReg(MISCREG_STATUS); + auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV); + if (pm == PRV_U || (pm == PRV_S && status.tvm == 1)) { + fault = make_shared( + "sfence in user mode or TVM enabled", + machInst); + } xc->tcBase()->getITBPtr()->demapPage(Rs1, Rs2); xc->tcBase()->getDTBPtr()->demapPage(Rs1, Rs2); }}, IsNonSpeculative, IsSerializeAfter, No_OpClass); diff --git a/src/arch/riscv/isa/formats/standard.isa b/src/arch/riscv/isa/formats/standard.isa index d80c671f2..11c06aa7e 100644 --- a/src/arch/riscv/isa/formats/standard.isa +++ b/src/arch/riscv/isa/formats/standard.isa @@ -307,6 +307,19 @@ def template CSRExecute {{ olddata = xc->readMiscReg(MISCREG_FFLAGS) | (xc->readMiscReg(MISCREG_FRM) << FRM_OFFSET); break; + case CSR_SATP: { + auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV); + STATUS status = xc->readMiscReg(MISCREG_STATUS); + if (pm == PRV_U || (pm == PRV_S && status.tvm == 1)) { + std::string error = csprintf( + "SATP access in user mode or with TVM enabled\n"); + fault = make_shared(error, machInst); + olddata = 0; + } else { + olddata = xc->readMiscReg(CSRData.at(csr).physIndex); + } + break; + } case CSR_MSTATUS: { auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV); if (pm != PrivilegeMode::PRV_M) {