From: lkcl Date: Mon, 21 Dec 2020 17:21:07 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~1079 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=33d783174270a147b57ab42b34cd6e9437e89ce8;p=libreriscv.git --- diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn index 071349985..56ca9e91a 100644 --- a/openpower/sv/svp_rewrite/svp64.mdwn +++ b/openpower/sv/svp_rewrite/svp64.mdwn @@ -53,6 +53,8 @@ As mentioned above, OE=1 is not applicable in SV, freeing this bit for alternati This leaves several Major Opcodes free for use by SV to fit alternative instructions: Vector Product, Vector Normalise, [[sv/mv.swizzle]], Texture LD/ST operations, and others critical to an efficient, effective 3D GPU and VPU ISA, and included as standard in other commercially-successful GPU ISAs. +Note however that svp64 is stand-alone and is in no way critically dependent on the existence or provision of 3D GPU or VPU instructions. These should be considered extensions. + # Register Naming and size SV Registers are simply the INT, FP and CR register files extended