From: Mark Shinwell Date: Wed, 28 May 2008 10:33:39 +0000 (+0000) Subject: mips.c (mips_cpu_info_table): Add loongson2e and loongson2f entries. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=33db2060b08b71034b5fb5eea16a87f473b32246;p=gcc.git mips.c (mips_cpu_info_table): Add loongson2e and loongson2f entries. 2008-05-28 Mark Shinwell * config/mips/mips.c (mips_cpu_info_table): Add loongson2e and loongson2f entries. (mips_rtx_cost_data): Add entries for Loongson-2E/2F. * config/mips/mips.h (processor_type): Add Loongson-2E and Loongson-2F entries. (TARGET_LOONGSON_2E, TARGET_LOONGSON_2F, TARGET_LOONGSON_2EF): New. (MIPS_ISA_LEVEL_SPEC): Handle Loongson-2E/2F. * config/mips/mips.md (define_attr cpu): Add loongson2e and loongson2f. * doc/invoke.texi (MIPS Options): Document loongson2e and loongson2f processor names. From-SVN: r136071 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c25c4380cb4..6af46e5e833 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,16 @@ +2008-05-28 Mark Shinwell + + * config/mips/mips.c (mips_cpu_info_table): Add loongson2e + and loongson2f entries. + (mips_rtx_cost_data): Add entries for Loongson-2E/2F. + * config/mips/mips.h (processor_type): Add Loongson-2E + and Loongson-2F entries. + (TARGET_LOONGSON_2E, TARGET_LOONGSON_2F, TARGET_LOONGSON_2EF): New. + (MIPS_ISA_LEVEL_SPEC): Handle Loongson-2E/2F. + * config/mips/mips.md (define_attr cpu): Add loongson2e and loongson2f. + * doc/invoke.texi (MIPS Options): Document loongson2e + and loongson2f processor names. + 2008-05-27 H.J. Lu PR target/35767 diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 6cb0d293dda..b12e2e24c62 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -584,6 +584,9 @@ static const struct mips_cpu_info mips_cpu_info_table[] = { { "r4600", PROCESSOR_R4600, 3, 0 }, { "orion", PROCESSOR_R4600, 3, 0 }, { "r4650", PROCESSOR_R4650, 3, 0 }, + /* ST Loongson 2E/2F processors. */ + { "loongson2e", PROCESSOR_LOONGSON_2E, 3, PTF_AVOID_BRANCHLIKELY }, + { "loongson2f", PROCESSOR_LOONGSON_2F, 3, PTF_AVOID_BRANCHLIKELY }, /* MIPS IV processors. */ { "r8000", PROCESSOR_R8000, 4, 0 }, @@ -832,6 +835,12 @@ static const struct mips_rtx_cost_data mips_rtx_cost_data[PROCESSOR_MAX] = { 1, /* branch_cost */ 4 /* memory_latency */ }, + { /* Loongson-2E */ + DEFAULT_COSTS + }, + { /* Loongson-2F */ + DEFAULT_COSTS + }, { /* M4k */ DEFAULT_COSTS }, diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 6d3c18feb46..402cd579c5c 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -47,6 +47,8 @@ enum processor_type { PROCESSOR_74KF2_1, PROCESSOR_74KF1_1, PROCESSOR_74KF3_2, + PROCESSOR_LOONGSON_2E, + PROCESSOR_LOONGSON_2F, PROCESSOR_M4K, PROCESSOR_R3900, PROCESSOR_R6000, @@ -237,6 +239,9 @@ enum mips_code_readable_setting { #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \ || mips_arch == PROCESSOR_SB1A) #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000) +#define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E) +#define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F) +#define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F) /* Scheduling target defines. */ #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000) @@ -646,7 +651,7 @@ enum mips_code_readable_setting { "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \ %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \ %{march=mips2|march=r6000:-mips2} \ - %{march=mips3|march=r4*|march=vr4*|march=orion:-mips3} \ + %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \ %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000:-mips4} \ %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \ %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \ diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 2b789eef8b6..592ad528042 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -415,7 +415,7 @@ ;; Attribute describing the processor. This attribute must match exactly ;; with the processor_type enumeration in mips.h. (define_attr "cpu" - "r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf2_1,24kf1_1,74kc,74kf2_1,74kf1_1,74kf3_2,m4k,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sb1a,sr71000" + "r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf2_1,24kf1_1,74kc,74kf2_1,74kf1_1,74kf3_2,loongson2e,loongson2f,m4k,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sb1a,sr71000" (const (symbol_ref "mips_tune"))) ;; The type of hardware hazard associated with this instruction. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index a2665f3c3b3..6dbd19ea2f9 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -11936,6 +11936,7 @@ The processor names are: @samp{24kec}, @samp{24kef2_1}, @samp{24kef1_1}, @samp{34kc}, @samp{34kf2_1}, @samp{34kf1_1}, @samp{74kc}, @samp{74kf2_1}, @samp{74kf1_1}, @samp{74kf3_2}, +@samp{loongson2e}, @samp{loongson2f}, @samp{m4k}, @samp{orion}, @samp{r2000}, @samp{r3000}, @samp{r3900}, @samp{r4000}, @samp{r4400},