From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Mon, 6 Feb 2012 16:45:40 +0000 (+0100)
Subject: top: connect UART IRQ
X-Git-Tag: 24jan2021_ls180~3260
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=33f1c456bfcb919c2580c12c7add0635c222fe5c;p=litex.git

top: connect UART IRQ
---

diff --git a/top.py b/top.py
index 3a28d54b..7014158e 100644
--- a/top.py
+++ b/top.py
@@ -39,7 +39,11 @@ def get():
 	uart0 = uart.UART(0, clk_freq, baud=115200)
 	csrcon0 = csr.Interconnect(wishbone2csr0.csr, [uart0.bank.interface])
 	
-	frag = autofragment.from_local()
+	interrupts = Fragment([
+		cpu0.interrupt[0].eq(uart0.events.irq)
+	])
+	
+	frag = autofragment.from_local() + interrupts
 	src_verilog, vns = verilog.convert(frag,
 		{clkfx_sys.clkin, reset0.trigger_reset},
 		name="soc",