From: whitequark <whitequark@whitequark.org>
Date: Wed, 3 Jul 2019 14:43:03 +0000 (+0000)
Subject: vendor: give names to IO buffer instances.
X-Git-Tag: locally_working~118
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=33f21628bb33f1ab6fa3d9dabe930d2650fe6ea8;p=nmigen.git

vendor: give names to IO buffer instances.

Fixes #123.
---

diff --git a/nmigen/vendor/lattice_ecp5.py b/nmigen/vendor/lattice_ecp5.py
index f6e2a9c..ee2cc11 100644
--- a/nmigen/vendor/lattice_ecp5.py
+++ b/nmigen/vendor/lattice_ecp5.py
@@ -261,7 +261,7 @@ class LatticeECP5Platform(TemplatedPlatform):
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
         for bit in range(len(port)):
-            m.submodules += Instance("IB",
+            m.submodules[pin.name] = Instance("IB",
                 i_I=port[bit],
                 o_O=i[bit]
             )
@@ -273,7 +273,7 @@ class LatticeECP5Platform(TemplatedPlatform):
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
         for bit in range(len(port)):
-            m.submodules += Instance("OB",
+            m.submodules[pin.name] = Instance("OB",
                 i_I=o[bit],
                 o_O=port[bit]
             )
@@ -285,7 +285,7 @@ class LatticeECP5Platform(TemplatedPlatform):
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
         for bit in range(len(port)):
-            m.submodules += Instance("OBZ",
+            m.submodules[pin.name] = Instance("OBZ",
                 i_T=t,
                 i_I=o[bit],
                 o_O=port[bit]
@@ -299,7 +299,7 @@ class LatticeECP5Platform(TemplatedPlatform):
         i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
                                                o_invert=True if invert else None)
         for bit in range(len(port)):
-            m.submodules += Instance("BB",
+            m.submodules[pin.name] = Instance("BB",
                 i_T=t,
                 i_I=o[bit],
                 o_O=i[bit],
@@ -313,7 +313,7 @@ class LatticeECP5Platform(TemplatedPlatform):
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
         for bit in range(len(p_port)):
-            m.submodules += Instance("IB",
+            m.submodules[pin.name] = Instance("IB",
                 i_I=p_port[bit],
                 o_O=i[bit]
             )
@@ -325,7 +325,7 @@ class LatticeECP5Platform(TemplatedPlatform):
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
         for bit in range(len(p_port)):
-            m.submodules += Instance("OB",
+            m.submodules[pin.name] = Instance("OB",
                 i_I=o[bit],
                 o_O=p_port[bit],
             )
@@ -337,7 +337,7 @@ class LatticeECP5Platform(TemplatedPlatform):
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
         for bit in range(len(p_port)):
-            m.submodules += Instance("OBZ",
+            m.submodules[pin.name] = Instance("OBZ",
                 i_T=t,
                 i_I=o[bit],
                 o_O=p_port[bit],
@@ -351,7 +351,7 @@ class LatticeECP5Platform(TemplatedPlatform):
         i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
                                                o_invert=True if invert else None)
         for bit in range(len(p_port)):
-            m.submodules += Instance("BB",
+            m.submodules[pin.name] = Instance("BB",
                 i_T=t,
                 i_I=o[bit],
                 o_O=i[bit],
diff --git a/nmigen/vendor/lattice_ice40.py b/nmigen/vendor/lattice_ice40.py
index 73db3aa..340a03a 100644
--- a/nmigen/vendor/lattice_ice40.py
+++ b/nmigen/vendor/lattice_ice40.py
@@ -248,9 +248,9 @@ class LatticeICE40Platform(TemplatedPlatform):
                 io_args.append(("i", "OUTPUT_ENABLE", pin.oe))
 
             if is_global_input:
-                m.submodules += Instance("SB_GB_IO", *io_args)
+                m.submodules[pin.name] = Instance("SB_GB_IO", *io_args)
             else:
-                m.submodules += Instance("SB_IO", *io_args)
+                m.submodules[pin.name] = Instance("SB_IO", *io_args)
 
     def get_input(self, pin, port, attrs, invert):
         self._check_feature("single-ended input", pin, attrs,
diff --git a/nmigen/vendor/xilinx_7series.py b/nmigen/vendor/xilinx_7series.py
index a24f664..3c43b08 100644
--- a/nmigen/vendor/xilinx_7series.py
+++ b/nmigen/vendor/xilinx_7series.py
@@ -239,7 +239,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
         for bit in range(len(port)):
-            m.submodules += Instance("IBUF",
+            m.submodules[pin.name] = Instance("IBUF",
                 i_I=port[bit],
                 o_O=i[bit]
             )
@@ -251,7 +251,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
         for bit in range(len(port)):
-            m.submodules += Instance("OBUF",
+            m.submodules[pin.name] = Instance("OBUF",
                 i_I=o[bit],
                 o_O=port[bit]
             )
@@ -263,7 +263,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
         for bit in range(len(port)):
-            m.submodules += Instance("OBUFT",
+            m.submodules[pin.name] = Instance("OBUFT",
                 i_T=t,
                 i_I=o[bit],
                 o_O=port[bit]
@@ -277,7 +277,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
         i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
                                                o_invert=True if invert else None)
         for bit in range(len(port)):
-            m.submodules += Instance("IOBUF",
+            m.submodules[pin.name] = Instance("IOBUF",
                 i_T=t,
                 i_I=o[bit],
                 o_O=i[bit],
@@ -291,7 +291,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
         for bit in range(len(p_port)):
-            m.submodules += Instance("IBUFDS",
+            m.submodules[pin.name] = Instance("IBUFDS",
                 i_I=p_port[bit], i_IB=n_port[bit],
                 o_O=i[bit]
             )
@@ -303,7 +303,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
         for bit in range(len(p_port)):
-            m.submodules += Instance("OBUFDS",
+            m.submodules[pin.name] = Instance("OBUFDS",
                 i_I=o[bit],
                 o_O=p_port[bit], o_OB=n_port[bit]
             )
@@ -315,7 +315,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
         for bit in range(len(p_port)):
-            m.submodules += Instance("OBUFTDS",
+            m.submodules[pin.name] = Instance("OBUFTDS",
                 i_T=t,
                 i_I=o[bit],
                 o_O=p_port[bit], o_OB=n_port[bit]
@@ -329,7 +329,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
         i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
                                                o_invert=True if invert else None)
         for bit in range(len(p_port)):
-            m.submodules += Instance("IOBUFDS",
+            m.submodules[pin.name] = Instance("IOBUFDS",
                 i_T=t,
                 i_I=o[bit],
                 o_O=i[bit],
diff --git a/nmigen/vendor/xilinx_spartan6.py b/nmigen/vendor/xilinx_spartan6.py
index 5128bf9..4a0d3a6 100644
--- a/nmigen/vendor/xilinx_spartan6.py
+++ b/nmigen/vendor/xilinx_spartan6.py
@@ -248,7 +248,7 @@ class XilinxSpartan6Platform(TemplatedPlatform):
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
         for bit in range(len(port)):
-            m.submodules += Instance("IBUF",
+            m.submodules[pin.name] = Instance("IBUF",
                 i_I=port[bit],
                 o_O=i[bit]
             )
@@ -260,7 +260,7 @@ class XilinxSpartan6Platform(TemplatedPlatform):
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
         for bit in range(len(port)):
-            m.submodules += Instance("OBUF",
+            m.submodules[pin.name] = Instance("OBUF",
                 i_I=o[bit],
                 o_O=port[bit]
             )
@@ -272,7 +272,7 @@ class XilinxSpartan6Platform(TemplatedPlatform):
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
         for bit in range(len(port)):
-            m.submodules += Instance("OBUFT",
+            m.submodules[pin.name] = Instance("OBUFT",
                 i_T=t,
                 i_I=o[bit],
                 o_O=port[bit]
@@ -286,7 +286,7 @@ class XilinxSpartan6Platform(TemplatedPlatform):
         i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
                                                o_invert=True if invert else None)
         for bit in range(len(port)):
-            m.submodules += Instance("IOBUF",
+            m.submodules[pin.name] = Instance("IOBUF",
                 i_T=t,
                 i_I=o[bit],
                 o_O=i[bit],
@@ -300,7 +300,7 @@ class XilinxSpartan6Platform(TemplatedPlatform):
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
         for bit in range(len(p_port)):
-            m.submodules += Instance("IBUFDS",
+            m.submodules[pin.name] = Instance("IBUFDS",
                 i_I=p_port[bit], i_IB=n_port[bit],
                 o_O=i[bit]
             )
@@ -312,7 +312,7 @@ class XilinxSpartan6Platform(TemplatedPlatform):
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
         for bit in range(len(p_port)):
-            m.submodules += Instance("OBUFDS",
+            m.submodules[pin.name] = Instance("OBUFDS",
                 i_I=o[bit],
                 o_O=p_port[bit], o_OB=n_port[bit]
             )
@@ -324,7 +324,7 @@ class XilinxSpartan6Platform(TemplatedPlatform):
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
         for bit in range(len(p_port)):
-            m.submodules += Instance("OBUFTDS",
+            m.submodules[pin.name] = Instance("OBUFTDS",
                 i_T=t,
                 i_I=o[bit],
                 o_O=p_port[bit], o_OB=n_port[bit]
@@ -338,7 +338,7 @@ class XilinxSpartan6Platform(TemplatedPlatform):
         i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
                                                o_invert=True if invert else None)
         for bit in range(len(p_port)):
-            m.submodules += Instance("IOBUFDS",
+            m.submodules[pin.name] = Instance("IOBUFDS",
                 i_T=t,
                 i_I=o[bit],
                 o_O=i[bit],