From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 24 Dec 2017 16:21:37 +0000 (+0100)
Subject: Bugfix in verilog_defaults argument parser
X-Git-Tag: yosys-0.8~242
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=34005348b65f69a2905357ee5877b5fbdd14da8c;p=yosys.git

Bugfix in verilog_defaults argument parser
---

diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index 19fc3c6af..e5917b97e 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -407,7 +407,7 @@ struct VerilogDefaults : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design*)
 	{
-		if (args.size() == 0)
+		if (args.size() < 2)
 			cmd_error(args, 1, "Missing argument.");
 
 		if (args[1] == "-add") {