From: Olof Kraigher Date: Sun, 12 Feb 2023 17:50:10 +0000 (+0100) Subject: Add vhdl_ls.toml dump to run.py X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=341a507486b0d088cd159e21f56c8681eafae13e;p=microwatt.git Add vhdl_ls.toml dump to run.py Signed-off-by: Olof Kraigher --- diff --git a/run.py b/run.py index a931cd6..5801e19 100755 --- a/run.py +++ b/run.py @@ -1,5 +1,6 @@ #!/usr/bin/env python3 +import json from pathlib import Path from vunit import VUnit @@ -15,11 +16,28 @@ PRJ.add_library("lib").add_source_files([ src_file for src_file in ROOT.glob("*.vhdl") # Use multiply.vhd and not xilinx-mult.vhd. Use VHDL-based random. - if not any(exclude in str(src_file) for exclude in ["xilinx-mult", "foreign_random", "nonrandom"]) + if not any(exclude in str(src_file) for exclude in ["xilinx-mult", "foreign_random", "nonrandom", "dmi_dtm_ecp5", "dmi_dtm_xilinx"]) ]) PRJ.add_library("unisim").add_source_files(ROOT / "sim-unisim" / "*.vhdl") PRJ.set_sim_option("disable_ieee_warnings", True) +def _gen_vhdl_ls(vu): + """ + Generate the vhdl_ls.toml file required by VHDL-LS language server. + """ + # Repo root + parent = Path(__file__).parent + + proj = vu._project + libs = proj.get_libraries() + + with open(parent / 'vhdl_ls.toml', "w") as f: + for lib in libs: + f.write(f"[libraries.{lib.name}]\n") + files = [str(file).replace('\\', '/') for file in lib._source_files] + f.write(f"files = {json.dumps(files, indent=4)}\n") + +_gen_vhdl_ls(PRJ) PRJ.main()