From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 12 Jun 2019 22:45:46 +0000 (-0700)
Subject: parse_xaiger to cope with inouts
X-Git-Tag: working-ls180~1237^2~143
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=342fc0a600584ab59fd24b6a6e22d49ff024c8d0;p=yosys.git

parse_xaiger to cope with inouts
---

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 0afdf9592..72b37d21d 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -696,10 +696,6 @@ void AigerReader::post_process()
 				RTLIL::Wire* wire = outputs[variable + co_count];
 				log_assert(wire);
 				log_assert(wire->port_output);
-				if (escaped_s.in("\\__dummy_o__", "\\__const0__", "\\__const1__")) {
-					wire->port_output = false;
-					continue;
-				}
 
 				if (index == 0) {
 					// Cope with the fact that a CO might be identical
@@ -797,8 +793,6 @@ void AigerReader::post_process()
 				port_output = port_output || other_wire->port_output;
 			}
 		}
-		if ((port_input && port_output) || (!port_input && !port_output))
-			continue;
 
 		wire = module->addWire(name, width);
 		wire->port_input = port_input;