From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 21 Aug 2019 01:22:58 +0000 (-0700)
Subject: Add reference to FD* timing
X-Git-Tag: working-ls180~1075^2^2~55
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=343039496baf434beca8c2fb3c275a60365f9496;p=yosys.git

Add reference to FD* timing
---

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index d879a56ee..6aba5a4b2 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -211,6 +211,8 @@ endmodule
 
 `endif
 
+// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250
+
 module FDRE ((* abc_arrival=303 *) output reg Q,
              input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;