From: Giacomo Gabrielli <Giacomo.Gabrielli@arm.com>
Date: Fri, 24 Jan 2014 21:29:30 +0000 (-0600)
Subject: cpu: Add support for Memory+Barrier instruction types in O3 cpu.
X-Git-Tag: stable_2014_08_26~199
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3436de0c2ad467c65066e48969a7c12bdbbb3d26;p=gem5.git

cpu: Add support for Memory+Barrier instruction types in O3 cpu.
---

diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index 8f0249ced..8eba028d6 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2012 ARM Limited
+ * Copyright (c) 2011-2013 ARM Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved.
  *
@@ -1157,11 +1157,17 @@ InstructionQueue<Impl>::doSquash(ThreadID tid)
             DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n",
                     tid, squashed_inst->seqNum, squashed_inst->pcState());
 
+            bool is_acq_rel = squashed_inst->isMemBarrier() &&
+                         (squashed_inst->isLoad() ||
+                           (squashed_inst->isStore() &&
+                             !squashed_inst->isStoreConditional()));
+
             // Remove the instruction from the dependency list.
-            if (!squashed_inst->isNonSpeculative() &&
-                !squashed_inst->isStoreConditional() &&
-                !squashed_inst->isMemBarrier() &&
-                !squashed_inst->isWriteBarrier()) {
+            if (is_acq_rel ||
+                (!squashed_inst->isNonSpeculative() &&
+                 !squashed_inst->isStoreConditional() &&
+                 !squashed_inst->isMemBarrier() &&
+                 !squashed_inst->isWriteBarrier())) {
 
                 for (int src_reg_idx = 0;
                      src_reg_idx < squashed_inst->numSrcRegs();