From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 1 Jan 2023 15:09:21 +0000 (+0000)
Subject: enable misaligned Mem in ISACaller by default
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3441e5d2b2aa6391b3a247e726faed964af806cd;p=openpower-isa.git

enable misaligned Mem in ISACaller by default
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 0d93f05e..accce0c2 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1173,7 +1173,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
         self.last_op_svshape = False
 
         # "raw" memory
-        self.mem = Mem(row_bytes=8, initial_mem=initial_mem)
+        self.mem = Mem(row_bytes=8, initial_mem=initial_mem, misaligned_ok=True)
         self.mem.log_fancy(kind=LogKind.InstrInOuts)
         self.imem = Mem(row_bytes=4, initial_mem=initial_insns)
         # MMU mode, redirect underlying Mem through RADIX