From: Connor Abbott <connor.w.abbott@intel.com>
Date: Thu, 13 Aug 2015 21:35:46 +0000 (-0700)
Subject: i965/vec4/nir: set the right type for 64-bit registers
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3457252b74f5490cff8915cac1e5fe0bf1031f5b;p=mesa.git

i965/vec4/nir: set the right type for 64-bit registers

Reviewed-by: Matt Turner <mattst88@gmail.com>
---

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index 062215dd6e3..bdee84b695c 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -142,6 +142,9 @@ vec4_visitor::nir_emit_impl(nir_function_impl *impl)
          reg->num_array_elems == 0 ? 1 : reg->num_array_elems;
       const unsigned num_regs = array_elems * DIV_ROUND_UP(reg->bit_size, 32);
       nir_locals[reg->index] = dst_reg(VGRF, alloc.allocate(num_regs));
+
+      if (reg->bit_size == 64)
+         nir_locals[reg->index].type = BRW_REGISTER_TYPE_DF;
    }
 
    nir_ssa_values = ralloc_array(mem_ctx, dst_reg, impl->ssa_alloc);