From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 25 Aug 2019 08:50:47 +0000 (+0100)
Subject: cleanup on msb1 and align: use Mux, remove out_do_z
X-Git-Tag: ls180-24jan2020~393
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=346473fa9bb4cf99ce42326f11fc0fed16f889b8;p=ieee754fpu.git

cleanup on msb1 and align: use Mux, remove out_do_z
---

diff --git a/src/ieee754/fpmul/align.py b/src/ieee754/fpmul/align.py
index f2559c2b..53ffeb3f 100644
--- a/src/ieee754/fpmul/align.py
+++ b/src/ieee754/fpmul/align.py
@@ -36,6 +36,10 @@ class FPAlignModSingle(PipeModBase):
         insel_a.m.name = "i_a_m"
         insel_b.m.name = "i_b_m"
 
+        # FPMSBHigh makes sure that the MSB is HI (duh).
+        # it does so (in a single cycle) by counting the leading zeros
+        # and performing a shift on the mantissa.  the same count is then
+        # subtracted from the exponent.
         mwid = self.o.z.m_width
         msb_a = FPMSBHigh(mwid, len(insel_a.e))
         msb_b = FPMSBHigh(mwid, len(insel_b.e))
@@ -48,9 +52,9 @@ class FPAlignModSingle(PipeModBase):
         comb += msb_b.m_in.eq(insel_b.m)
         comb += msb_b.e_in.eq(insel_b.e)
 
-        # copy input to output (overridden below)
-        comb += self.o.a.eq(insel_a)
-        comb += self.o.b.eq(insel_b)
+        # copy input to output sign
+        comb += self.o.a.s.eq(insel_a.s)
+        comb += self.o.b.s.eq(insel_b.s)
 
         # normalisation increase/decrease conditions
         decrease_a = Signal(reset_less=True)
@@ -59,17 +63,14 @@ class FPAlignModSingle(PipeModBase):
         comb += decrease_b.eq(insel_b.m_msbzero)
 
         # ok this is near-identical to FPNorm: use same class (FPMSBHigh)
-        with m.If(~self.i.out_do_z):
-            with m.If(decrease_a):
-                comb += [
-                    self.o.a.e.eq(msb_a.e_out),
-                    self.o.a.m.eq(msb_a.m_out),
-                ]
-            with m.If(decrease_b):
-                comb += [
-                    self.o.b.e.eq(msb_b.e_out),
-                    self.o.b.m.eq(msb_b.m_out),
-                ]
+        comb += [
+            self.o.a.e.eq(Mux(decrease_a, msb_a.e_out, insel_a.e)),
+            self.o.a.m.eq(Mux(decrease_a, msb_a.m_out, insel_a.m))
+            ]
+        comb += [
+            self.o.b.e.eq(Mux(decrease_b, msb_b.e_out, insel_b.e)),
+            self.o.b.m.eq(Mux(decrease_b, msb_b.m_out, insel_b.m))
+            ]
 
         comb += self.o.ctx.eq(self.i.ctx)
         comb += self.o.out_do_z.eq(self.i.out_do_z)
diff --git a/src/ieee754/fpmul/mul0.py b/src/ieee754/fpmul/mul0.py
index 97821a65..6b00762a 100644
--- a/src/ieee754/fpmul/mul0.py
+++ b/src/ieee754/fpmul/mul0.py
@@ -32,16 +32,14 @@ class FPMulStage0Mod(PipeModBase):
         # store intermediate tests (and zero-extended mantissas)
         am0 = Signal(len(self.i.a.m)+1, reset_less=True)
         bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
-        comb += [
-                     am0.eq(Cat(self.i.a.m, 0)),
+        comb += [ am0.eq(Cat(self.i.a.m, 0)),
                      bm0.eq(Cat(self.i.b.m, 0))
-                    ]
-        # same-sign (both negative or both positive) mul mantissas
-        with m.If(~self.i.out_do_z):
-            comb += [self.o.z.e.eq(self.i.a.e + self.i.b.e + 1),
-                         self.o.product.eq(am0 * bm0 * 4),
-                         self.o.z.s.eq(self.i.a.s ^ self.i.b.s)
                 ]
+        # same-sign (both negative or both positive) mul mantissas
+        comb += [self.o.z.e.eq(self.i.a.e + self.i.b.e + 1),
+                     self.o.product.eq(am0 * bm0 * 4),
+                     self.o.z.s.eq(self.i.a.s ^ self.i.b.s)
+        ]
 
         comb += self.o.oz.eq(self.i.oz)
         comb += self.o.out_do_z.eq(self.i.out_do_z)