From: Anton Blanchard Date: Mon, 9 Aug 2021 00:29:48 +0000 (+1000) Subject: litedram: Fix compiler warning X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=346686feb8b094e1783aa105ce444d4e4cc6e0a1;p=microwatt.git litedram: Fix compiler warning define MAIN_RAM_BASE and MAIN_RAM_SIZE as unsigned long Signed-off-by: Anton Blanchard --- diff --git a/litedram/gen-src/generate.py b/litedram/gen-src/generate.py index 182c2d1..a6018c6 100755 --- a/litedram/gen-src/generate.py +++ b/litedram/gen-src/generate.py @@ -35,7 +35,7 @@ def build_init_code(build_dir, is_sim): print(" lx src dir:", lxbios_src_dir) # Generate mem.h (hard wire size, it's not important) - mem_h = "#define MAIN_RAM_BASE 0x40000000\n#define MAIN_RAM_SIZE 0x10000000" + mem_h = "#define MAIN_RAM_BASE 0x40000000UL\n#define MAIN_RAM_SIZE 0x10000000UL\n" write_to_file(os.path.join(gen_inc_dir, "mem.h"), mem_h) # Environment