From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Fri, 11 Aug 2017 23:55:31 +0000 (-0700)
Subject: Fixed typo in GP_COUNT8 sim model
X-Git-Tag: yosys-0.8~346^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=348acbd968193d6daaf53a16147b9bea932c92fb;p=yosys.git

Fixed typo in GP_COUNT8 sim model
---

diff --git a/techlibs/greenpak4/cells_sim_digital.v b/techlibs/greenpak4/cells_sim_digital.v
index cda83862a..3ed80005b 100644
--- a/techlibs/greenpak4/cells_sim_digital.v
+++ b/techlibs/greenpak4/cells_sim_digital.v
@@ -411,7 +411,7 @@ module GP_COUNT8(
 	//Combinatorially output underflow flag whenever we wrap low
 	always @(*) begin
 		OUT <= (count == 8'h0);
-		OUT <= count;
+		POUT <= count;
 	end
 
 	//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.