From: Kevin Lim <ktlim@umich.edu>
Date: Tue, 12 Dec 2006 04:51:21 +0000 (-0500)
Subject: Fix up in case a req hasn't yet been generated for this instruction (if there was... 
X-Git-Tag: m5_2.0_beta3~275^2~6
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=34924ce3b82ec19322990c721369b08ddfd3df8a;p=gem5.git

Fix up in case a req hasn't yet been generated for this instruction (if there was a fault prior to translation).

--HG--
extra : convert_revision : 43f4ea5e6a234cc6071006eab72135c11b8523c8
---

diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 4facea9f9..3b84d3411 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -418,7 +418,8 @@ LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
         // realizes there is activity.
         // Mark it as executed unless it is an uncached load that
         // needs to hit the head of commit.
-        if (!(inst->req->isUncacheable()) || inst->isAtCommit()) {
+        if (!(inst->req && inst->req->isUncacheable()) ||
+            inst->isAtCommit()) {
             inst->setExecuted();
         }
         iewStage->instToCommit(inst);