From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 29 Aug 2019 02:59:09 +0000 (-0700)
Subject: read_verilog -defer should still populate module attributes
X-Git-Tag: working-ls180~1078^2~8
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=34ae29295db53289e786c0279ed00474cf0294d3;p=yosys.git

read_verilog -defer should still populate module attributes
---

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 82283fb5b..6a91c418b 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -1073,11 +1073,6 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
 
 		ignoreThisSignalsInInitial = RTLIL::SigSpec();
 
-		for (auto &attr : ast->attributes) {
-			if (attr.second->type != AST_CONSTANT)
-				log_file_error(ast->filename, ast->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
-			current_module->attributes[attr.first] = attr.second->asAttrConst();
-		}
 		for (size_t i = 0; i < ast->children.size(); i++) {
 			AstNode *node = ast->children[i];
 			if (node->type == AST_WIRE || node->type == AST_MEMORY)
@@ -1100,6 +1095,12 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
 		ignoreThisSignalsInInitial = RTLIL::SigSpec();
 	}
 
+	for (auto &attr : ast->attributes) {
+		if (attr.second->type != AST_CONSTANT)
+			log_file_error(ast->filename, ast->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
+		current_module->attributes[attr.first] = attr.second->asAttrConst();
+	}
+
 	if (ast->type == AST_INTERFACE)
 		current_module->set_bool_attribute("\\is_interface");
 	current_module->ast = ast_before_simplify;