From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 17 Jul 2020 19:18:23 +0000 (+0100)
Subject: forward-port minerva loadstore bugfix
X-Git-Tag: semi_working_ecp5~701^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=34b007434a2fa5d46c678883289ab17dc88363a0;p=soc.git

forward-port minerva loadstore bugfix
commit a03a72e04764dc976d85ea44b1cf0767e240b81f
Author: Jean-François Nguyen <jf@lambdaconcept.com>
Date:   Thu Apr 30 12:23:36 2020 +0200

    loadstore: fix conflict between write buffer and dcache refill.
---

diff --git a/src/soc/minerva/units/loadstore.py b/src/soc/minerva/units/loadstore.py
index f3ca09d7..a4d76d19 100644
--- a/src/soc/minerva/units/loadstore.py
+++ b/src/soc/minerva/units/loadstore.py
@@ -184,22 +184,21 @@ class CachedLoadStoreUnit(LoadStoreUnitInterface, Elaboratable):
         m.d.comb += dba.bus.connect(self.dbus)
 
         wrbuf_port = dbus_arbiter.port(priority=0)
-        with m.If(wrbuf_port.cyc):
+        m.d.comb += [
+            wrbuf_port.cyc.eq(wrbuf.r_rdy),
+            wrbuf_port.we.eq(Const(1)),
+        ]
+        with m.If(wrbuf_port.stb):
             with m.If(wrbuf_port.ack | wrbuf_port.err):
-                m.d.sync += [
-                    wrbuf_port.cyc.eq(0),
-                    wrbuf_port.stb.eq(0)
-                ]
+                m.d.sync += wrbuf_port.stb.eq(0)
                 m.d.comb += wrbuf.r_en.eq(1)
         with m.Elif(wrbuf.r_rdy):
             m.d.sync += [
-                wrbuf_port.cyc.eq(1),
                 wrbuf_port.stb.eq(1),
                 wrbuf_port.adr.eq(wrbuf_r_data.addr),
                 wrbuf_port.sel.eq(wrbuf_r_data.mask),
                 wrbuf_port.dat_w.eq(wrbuf_r_data.data)
             ]
-        m.d.comb += wrbuf_port.we.eq(Const(1))
 
         dcache_port = dba.port(priority=1)
         cti = Mux(dcache.bus_last, Cycle.END, Cycle.INCREMENT)