From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 13 Apr 2023 08:55:49 +0000 (+0100)
Subject: add ldst-shifted-postinc (!) to ls012 optable, starting to get hairy
X-Git-Tag: opf_rfc_ls010_v1~18
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=34b3cb2e599181d75550244ca5440b243ae245d2;p=libreriscv.git

add ldst-shifted-postinc (!) to ls012 optable, starting to get hairy
---

diff --git a/openpower/sv/rfc/ls012/optable.csv b/openpower/sv/rfc/ls012/optable.csv
index 24ff3a711..dfcf382f4 100644
--- a/openpower/sv/rfc/ls012/optable.csv
+++ b/openpower/sv/rfc/ls012/optable.csv
@@ -21,13 +21,42 @@ stdup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
 stdupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
 # FP LD/ST-Postincrement
 lfdu,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
-lfsu,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
-lfdux,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
-lsdux,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
-stfdu,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
-stfsu,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
-stfdux,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
-stfsux,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
+lfsup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
+lfdupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
+lsdupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
+stfdup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
+stfsup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
+stfdupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
+stfsupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
+# LD/ST-Shifted-Postincrement
+lbzusp,    ls011, low, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
+lbzuspx,   ls011, med, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
+lhzusp,    ls011, low, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
+lhzuspx,   ls011, med, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
+lhausp,    ls011, low, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
+lhauspx,   ls011, med, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
+lwzusp,    ls011, low, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
+lwzuspx,   ls011, med, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
+lwauspx,   ls011, med, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
+ldusp,     ls011, low, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
+lduspx,    ls011, med, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
+stbusp,    ls011, low, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
+stbuspx,   ls011, med, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
+sthusp,    ls011, low, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
+sthuspx,   ls011, med, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
+stwusp,    ls011, low, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
+stwuspx,   ls011, med, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
+stdusp,    ls011, low, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
+stduspx,   ls011, med, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
+# FP LD/ST-Shifted-Postincrement
+lfdups,    ls011, low, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
+lfsups,    ls011, low, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
+lfdupsx,   ls011, med, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
+lsdupsx,   ls011, med, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
+stfdups,    ls011, low, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
+stfsups,    ls011, low, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
+stfdupsx,   ls011, med, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
+stfsupsx,   ls011, med, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
 # LD/ST-Index-Shifted (w/Update)
 lbzsx,    ls004, high, 9, yes, EXT0xx, no, ls004, 2R1W
 lbzusx,    ls004, high, 9, yes, EXT0xx, no, ls004, 2R2W