From: Samuel Pitoiset Date: Wed, 2 Oct 2019 18:37:43 +0000 (+0200) Subject: radv: fix build X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=34be977f80da67d3fb8cfc8bec04104e03cfe19d;p=mesa.git radv: fix build Forgot to amend the commit before updating the MR. Signed-off-by: Samuel Pitoiset --- diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 0d14ba2eda6..f8dd6178733 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -3445,7 +3445,7 @@ radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs, S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE); if (!pCreateInfo->pRasterizationState->depthClampEnable && - ps->info.info.ps.writes_z) { + ps->info.ps.writes_z) { /* From VK_EXT_depth_range_unrestricted spec: * * "The behavior described in Primitive Clipping still applies.