From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 17 Oct 2014 04:02:38 +0000 (+0200)
Subject: Fixed a few VS warnings
X-Git-Tag: yosys-0.4~43
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=34caeeb4f3e21d8da3b75682e48ab85c27021b82;p=yosys.git

Fixed a few VS warnings
---

diff --git a/kernel/log.h b/kernel/log.h
index 421c50d3f..10250cb9d 100644
--- a/kernel/log.h
+++ b/kernel/log.h
@@ -181,7 +181,7 @@ struct PerformanceTimer
 	}
 
 	float sec() const {
-		return total_ns * 1e-9;
+		return total_ns * 1e-9f;
 	}
 #else
 	static int64_t query() { return 0; }
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 5629c8652..8a4d348be 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -898,7 +898,7 @@ struct RTLIL::SigBit
 	SigBit() : wire(NULL), data(RTLIL::State::S0) { }
 	SigBit(RTLIL::State bit) : wire(NULL), data(bit) { }
 	SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_assert(wire && wire->width == 1); }
-	SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire); }
+	SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire != nullptr); }
 	SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; }
 	SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data[index]; }
 	SigBit(const RTLIL::SigSpec &sig);
diff --git a/kernel/satgen.h b/kernel/satgen.h
index d556f4f32..2c69663c4 100644
--- a/kernel/satgen.h
+++ b/kernel/satgen.h
@@ -107,7 +107,7 @@ struct SatGen
 	{
 		log_assert(timestep != 0);
 		std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
-		return imported_signals[pf].count(bit);
+		return imported_signals[pf].count(bit) != 0;
 	}
 
 	void getAsserts(RTLIL::SigSpec &sig_a, RTLIL::SigSpec &sig_en, int timestep = -1)