From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 12 Mar 2021 21:41:57 +0000 (+0000)
Subject: add ability to set and distinguish RT=0 (RT_OR_ZERO) to OutSel enum
X-Git-Tag: convert-csv-opcode-to-binary~47
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=34cfb7fdb5f6e7647c78ff45b914723256a9c417;p=soc.git

add ability to set and distinguish RT=0 (RT_OR_ZERO) to OutSel enum
---

diff --git a/src/soc/decoder/power_enums.py b/src/soc/decoder/power_enums.py
index 1254534d..a823295c 100644
--- a/src/soc/decoder/power_enums.py
+++ b/src/soc/decoder/power_enums.py
@@ -352,6 +352,7 @@ class OutSel(Enum):
     RT = 1
     RA = 2
     SPR = 3
+    RT_OR_ZERO = 4
 
 
 @unique