From: Alex Deucher <alexander.deucher@amd.com>
Date: Thu, 15 Nov 2012 14:31:26 +0000 (-0500)
Subject: radeonsi: assert that the DB format is valid (v2)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=34d487b64d467a568d197de8376dcba88418bea1;p=mesa.git

radeonsi: assert that the DB format is valid (v2)

Assert that the DB format is valid and default to
the INVALID hw format rather than ~0U when the format
doesn't match for non-debug builds.

v2: use INVALID hw format rather than ~0U

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
---

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index e7a4005ee06..fbc636dece4 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1109,7 +1109,7 @@ static uint32_t si_translate_dbformat(enum pipe_format format)
 	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 		return V_028040_Z_32_FLOAT;
 	default:
-		return ~0U;
+		return V_028040_Z_INVALID;
 	}
 }
 
@@ -1438,7 +1438,7 @@ static bool si_is_colorbuffer_format_supported(enum pipe_format format)
 
 static bool si_is_zs_format_supported(enum pipe_format format)
 {
-	return si_translate_dbformat(format) != ~0U;
+	return si_translate_dbformat(format) != V_028040_Z_INVALID;
 }
 
 boolean si_is_format_supported(struct pipe_screen *screen,
@@ -1687,6 +1687,8 @@ static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4,
 
 	format = si_translate_dbformat(rtex->real_format);
 
+	assert(format != V_028040_Z_INVALID);
+
 	z_offs = r600_resource_va(rctx->context.screen, surf->base.texture);
 	z_offs += rtex->surface.level[level].offset;
 
@@ -1739,12 +1741,7 @@ static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4,
 		       S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
 
 	si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, 0x1);
-	if (format != ~0U) {
-		si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
-
-	} else {
-		si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0);
-	}
+	si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
 
 	if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
 		si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info);