From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 20 Apr 2020 16:38:29 +0000 (-0700)
Subject: abc9: add testcase reduced from #1970
X-Git-Tag: working-ls180~614^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=34d8ff8b569262da28175b56099e099413313022;p=yosys.git

abc9: add testcase reduced from #1970
---

diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys
index 0c7695089..6e2415ad7 100644
--- a/tests/various/abc9.ys
+++ b/tests/various/abc9.ys
@@ -53,3 +53,22 @@ assign q = w;
 endmodule
 EOT
 abc9 -lut 4 -dff
+
+
+design -reset
+read_verilog -icells -specify <<EOT
+(* abc9_lut=1, blackbox *)
+module LUT2(input [1:0] i, output o);
+parameter [3:0] mask = 0;
+assign o = i[0] ? (i[1] ? mask[3] : mask[2])
+                : (i[1] ? mask[1] : mask[0]);
+specify
+  (i *> o) = 1;
+endspecify
+endmodule
+
+module top(input [1:0] i, output o);
+LUT2 #(.mask(4'b0)) lut (.i(i), .o(o));
+endmodule
+EOT
+abc9