From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 23 Jul 2019 21:26:13 +0000 (+0100)
Subject: reduce next_bits by 1
X-Git-Tag: ls180-24jan2020~741
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=34db1ccbb8c1f6759b046662897c6e8f532c9e5c;p=ieee754fpu.git

reduce next_bits by 1
---

diff --git a/src/ieee754/div_rem_sqrt_rsqrt/core.py b/src/ieee754/div_rem_sqrt_rsqrt/core.py
index 7c6fb181..13321698 100644
--- a/src/ieee754/div_rem_sqrt_rsqrt/core.py
+++ b/src/ieee754/div_rem_sqrt_rsqrt/core.py
@@ -416,7 +416,7 @@ class DivPipeCoreCalculateStage(Elaboratable):
         # compare_lhs >= compare_rhs is a pipeline invariant).
 
         m.submodules.pe = pe = PriorityEncoder(radix)
-        next_bits = Signal(log2_radix+1, reset_less=True)
+        next_bits = Signal(log2_radix, reset_less=True)
         m.d.comb += pe.i.eq(~pass_flags)
         with m.If(~pe.n):
             m.d.comb += next_bits.eq(pe.o-1)