From: Gert Wollny Date: Sun, 10 May 2020 11:38:17 +0000 (+0200) Subject: r600/sfn: Take SSBO buffer ID offset into account X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=34e15cd610c1b24d63e0ee2293517f834503a80d;p=mesa.git r600/sfn: Take SSBO buffer ID offset into account Signed-off-by: Gert Wollny Part-of: --- diff --git a/src/gallium/drivers/r600/sfn/sfn_emitssboinstruction.cpp b/src/gallium/drivers/r600/sfn/sfn_emitssboinstruction.cpp index e9510eb614b..f7eb09936a4 100644 --- a/src/gallium/drivers/r600/sfn/sfn_emitssboinstruction.cpp +++ b/src/gallium/drivers/r600/sfn/sfn_emitssboinstruction.cpp @@ -13,10 +13,16 @@ namespace r600 { EmitSSBOInstruction::EmitSSBOInstruction(ShaderFromNirProcessor& processor): EmitInstruction(processor), - m_require_rat_return_address(false) + m_require_rat_return_address(false), + m_ssbo_image_offset(0) { } +void EmitSSBOInstruction::set_ssbo_offset(int offset) +{ + m_ssbo_image_offset = offset; +} + void EmitSSBOInstruction::set_require_rat_return_address() { @@ -329,7 +335,7 @@ bool EmitSSBOInstruction::emit_store_ssbo(const nir_intrinsic_instr* instr) (1 << nir_src_num_components(instr->src[0])) - 1, {0,1,2,3}, true); emit_instruction(new RatInstruction(cf_mem_rat, RatInstruction::STORE_TYPED, - values, addr_vec, 0, rat_id, 1, + values, addr_vec, m_ssbo_image_offset, rat_id, 1, 1, 0, false)); for (unsigned i = 1; i < nir_src_num_components(instr->src[0]); ++i) { emit_instruction(new AluInstruction(op1_mov, values.reg_i(0), from_nir(instr->src[0], i), write)); @@ -391,7 +397,7 @@ EmitSSBOInstruction::emit_ssbo_atomic_op(const nir_intrinsic_instr *intrin) GPRVector out_vec({coord, coord, coord, coord}); - auto atomic = new RatInstruction(cf_mem_rat, opcode, m_rat_return_address, out_vec, imageid, + auto atomic = new RatInstruction(cf_mem_rat, opcode, m_rat_return_address, out_vec, imageid + m_ssbo_image_offset, image_offset, 1, 0xf, 0, true); emit_instruction(atomic); emit_instruction(new WaitAck(0)); @@ -474,9 +480,18 @@ bool EmitSSBOInstruction::fetch_return_value(const nir_intrinsic_instr *intrin) unsigned format_comp = 0; unsigned endian = 0; + int imageid = 0; + PValue image_offset; + + if (nir_src_is_const(intrin->src[0])) + imageid = nir_src_as_int(intrin->src[0]); + else + image_offset = from_nir(intrin->src[0], 0); + r600_vertex_data_type(format, &fmt, &num_format, &format_comp, &endian); GPRVector dest = vec_from_nir(intrin->dest, nir_dest_num_components(intrin->dest)); + auto fetch = new FetchInstruction(vc_fetch, no_index_offset, (EVTXDataFormat)fmt, @@ -486,8 +501,8 @@ bool EmitSSBOInstruction::fetch_return_value(const nir_intrinsic_instr *intrin) dest, 0, false, - 0x3, - R600_IMAGE_IMMED_RESOURCE_OFFSET, + 0xf, + R600_IMAGE_IMMED_RESOURCE_OFFSET + imageid, 0, bim_none, false, @@ -495,8 +510,7 @@ bool EmitSSBOInstruction::fetch_return_value(const nir_intrinsic_instr *intrin) 0, 0, 0, - PValue(), - {0,1,2,3}); + image_offset, {0,1,2,3}); fetch->set_flag(vtx_srf_mode); fetch->set_flag(vtx_use_tc); if (format_comp) diff --git a/src/gallium/drivers/r600/sfn/sfn_emitssboinstruction.h b/src/gallium/drivers/r600/sfn/sfn_emitssboinstruction.h index 98479da30b2..5064845d530 100644 --- a/src/gallium/drivers/r600/sfn/sfn_emitssboinstruction.h +++ b/src/gallium/drivers/r600/sfn/sfn_emitssboinstruction.h @@ -10,6 +10,8 @@ class EmitSSBOInstruction: public EmitInstruction { public: EmitSSBOInstruction(ShaderFromNirProcessor& processor); + void set_ssbo_offset(int offset); + void set_require_rat_return_address(); bool load_rat_return_address(); bool load_atomic_inc_limits(); @@ -42,6 +44,7 @@ private: bool m_require_rat_return_address; GPRVector m_rat_return_address; + int m_ssbo_image_offset; }; } diff --git a/src/gallium/drivers/r600/sfn/sfn_shader_base.cpp b/src/gallium/drivers/r600/sfn/sfn_shader_base.cpp index a1a258c8cbd..152fd3c52e8 100644 --- a/src/gallium/drivers/r600/sfn/sfn_shader_base.cpp +++ b/src/gallium/drivers/r600/sfn/sfn_shader_base.cpp @@ -74,7 +74,8 @@ ShaderFromNirProcessor::ShaderFromNirProcessor(pipe_shader_type ptype, m_scratch_size(scratch_size), m_next_hwatomic_loc(0), m_sel(sel), - m_atomic_base(atomic_base) + m_atomic_base(atomic_base), + m_image_count(0) { m_sh_info.processor_type = ptype; @@ -151,6 +152,10 @@ enum chip_class ShaderFromNirProcessor::get_chip_class(void) const bool ShaderFromNirProcessor::allocate_reserved_registers() { bool retval = do_allocate_reserved_registers(); + m_ssbo_instr.load_rat_return_address(); + if (sh_info().uses_atomics) + m_ssbo_instr.load_atomic_inc_limits(); + m_ssbo_instr.set_ssbo_offset(m_image_count); return retval; } @@ -260,6 +265,10 @@ bool ShaderFromNirProcessor::process_uniforms(nir_variable *uniform) sh_info().uses_images = 1; } + if (uniform->type->is_image()) { + ++m_image_count; + } + return true; } diff --git a/src/gallium/drivers/r600/sfn/sfn_shader_base.h b/src/gallium/drivers/r600/sfn/sfn_shader_base.h index 878e5b7e87d..11c403d15bb 100644 --- a/src/gallium/drivers/r600/sfn/sfn_shader_base.h +++ b/src/gallium/drivers/r600/sfn/sfn_shader_base.h @@ -208,6 +208,7 @@ private: r600_pipe_shader_selector& m_sel; int m_atomic_base ; + int m_image_count; }; }