From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 25 May 2021 11:37:47 +0000 (+0000)
Subject: rename pll out signal to out_v in "fake" pll cell
X-Git-Tag: LS180_RC3~49
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=34eaf7feae8e6835b69fbb7b1582dd0b9905f2ef;p=soclayout.git

rename pll out signal to out_v in "fake" pll cell
---

diff --git a/experiments9/pll.py b/experiments9/pll.py
index 0bc3cff..86944b3 100644
--- a/experiments9/pll.py
+++ b/experiments9/pll.py
@@ -220,14 +220,15 @@ def _load():
             'a0': Net.create(cell, 'a0'),
             'a1': Net.create(cell, 'a1'),
             'vco_test_ana': Net.create(cell, 'vco_test_ana'),
-            'out': Net.create(cell, 'out'),
+            'out_v': Net.create(cell, 'out_v'),
         }
 
         # create series of stepped pins
         x = 0.135*20
         wid = 0.135 / 2
         step = wid*10
-        for cname in ['ref', 'div_out_test', 'a0', 'a1', 'vco_test_ana', 'out']:
+        for cname in ['ref', 'div_out_test', 'a0', 'a1', 'vco_test_ana',
+                      'out_v']:
             net = nets[cname]
             pin = Vertical.create(
                 net, tech.getLayer('metal1'),