From: Kelvin Nilsen Date: Fri, 12 Apr 2019 12:51:58 +0000 (+0000) Subject: re PR target/87532 (bad results from vec_extract(unsigned char, foo) dependent upon... X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=34f02c07fb1a9d966fb7af5a8c28c213e84d89c5;p=gcc.git re PR target/87532 (bad results from vec_extract(unsigned char, foo) dependent upon function inline) gcc/ChangeLog: 2019-04-12 Kelvin Nilsen PR target/87532 * config/rs6000/rs6000.c (rs6000_split_vec_extract_var): Use inner mode of vector rather than mode of destination for move instruction. * config/rs6000/vsx.md (*vsx_extract__mode_var): Use QI inner mode with V16QI vector mode. gcc/testsuite/ChangeLog: 2019-04-12 Kelvin Nilsen PR target/87532 * gcc.target/powerpc/fold-vec-extract-char.p8.c: Adjust expected instruction counts. * gcc.target/powerpc/fold-vec-extract-int.p8.c: Likewise. * gcc.target/powerpc/fold-vec-extract-short.p8.c: Likewise. From-SVN: r270313 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index dbda8ac5fab..2790eab6690 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2019-04-12 Kelvin Nilsen + + PR target/87532 + * config/rs6000/rs6000.c (rs6000_split_vec_extract_var): Use inner + mode of vector rather than mode of destination for move instruction. + * config/rs6000/vsx.md (*vsx_extract__mode_var): + Use QI inner mode with V16QI vector mode. + 2019-04-12 Jakub Jelinek PR target/52726 diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index d16dd24b1d6..9105253d763 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -7167,7 +7167,7 @@ rs6000_split_vec_extract_var (rtx dest, rtx src, rtx element, rtx tmp_gpr, rtx tmp_altivec) { machine_mode mode = GET_MODE (src); - machine_mode scalar_mode = GET_MODE (dest); + machine_mode scalar_mode = GET_MODE_INNER (GET_MODE (src)); unsigned scalar_size = GET_MODE_SIZE (scalar_mode); int byte_shift = exact_log2 (scalar_size); diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index f81d5fb1009..607c0cd33f2 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -3739,9 +3739,9 @@ DONE; }) -(define_insn_and_split "*vsx_extract___var" - [(set (match_operand:SDI 0 "gpc_reg_operand" "=r,r,r") - (zero_extend:SDI +(define_insn_and_split "*vsx_extract__mode_var" + [(set (match_operand: 0 "gpc_reg_operand" "=r,r,r") + (zero_extend: (unspec: [(match_operand:VSX_EXTRACT_I 1 "input_operand" "wK,v,m") (match_operand:DI 2 "gpc_reg_operand" "r,r,r")] @@ -3753,7 +3753,7 @@ "&& reload_completed" [(const_int 0)] { - machine_mode smode = mode; + machine_mode smode = mode; rs6000_split_vec_extract_var (gen_rtx_REG (smode, REGNO (operands[0])), operands[1], operands[2], operands[3], operands[4]); diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index fe02e42e21d..1c212b46041 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,11 @@ +2019-04-12 Kelvin Nilsen + + PR target/87532 + * gcc.target/powerpc/fold-vec-extract-char.p8.c: Adjust expected + instruction counts. + * gcc.target/powerpc/fold-vec-extract-int.p8.c: Likewise. + * gcc.target/powerpc/fold-vec-extract-short.p8.c: Likewise. + 2019-04-12 Jakub Jelinek PR c/89946 diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p8.c index 81a7a0239f1..f3fea467a5b 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p8.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p8.c @@ -6,9 +6,9 @@ /* { dg-options "-mdejagnu-cpu=power8 -O2" } */ // six tests total. Targeting P8LE / P8BE. -// P8 LE variable offset: rldicl, subfic, sldi, mtvsrd, xxpermdi, vslo, mfvsrd, sradi, (extsb) +// P8 LE variable offset: rldicl, subfic, sldi, mtvsrd, xxpermdi, vslo, mfvsrd, sradi, rlwinm, (extsb) // P8 LE constant offset: vspltb, mfvsrd, rlwinm, (extsb) -// P8 BE variable offset: sldi, mtvsrd, xxpermdi, vslo, mfvsrd, sradi, (extsb) +// P8 BE variable offset: sldi, mtvsrd, xxpermdi, vslo, mfvsrd, sradi, rlwinm, (extsb) // P8 BE constant offset: vspltb, mfvsrd, rlwinm, (extsb) /* { dg-final { scan-assembler-times {\mrldicl\M} 3 { target { le } } } } */ @@ -21,12 +21,12 @@ /* { dg-final { scan-assembler-times {\msrdi\M} 3 { target lp64 } } } */ /* { dg-final { scan-assembler-times "extsb" 2 } } */ /* { dg-final { scan-assembler-times {\mvspltb\M} 3 { target lp64 } } } */ -/* { dg-final { scan-assembler-times {\mrlwinm\M} 2 { target lp64} } } */ +/* { dg-final { scan-assembler-times {\mrlwinm\M} 4 { target lp64 } } } */ /* multiple codegen variations for -m32. */ -/* { dg-final { scan-assembler-times {\mrlwinm\M} 3 { target ilp32} } } */ -/* { dg-final { scan-assembler-times {\mstxvw4x\M} 6 { target ilp32} } } */ -/* { dg-final { scan-assembler-times {\mlbz\M} 6 { target ilp32} } } */ +/* { dg-final { scan-assembler-times {\mrlwinm\M} 3 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {\mstxvw4x\M} 6 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {\mlbz\M} 6 { target ilp32 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c index 637cdce318a..83ce4ee0829 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c @@ -7,14 +7,14 @@ // Targeting P8 (LE) and (BE). 6 tests total. // P8 LE constant: vspltw, mfvsrwz, (1:extsw/2:rldicl) -// P8 LE variables: rldicl, subfic, sldi, mtvsrd, xxpermdi, vslo, mfvsrd, sradi, (1:extsw) +// P8 LE variables: subfic, sldi, mtvsrd, xxpermdi, vslo, mfvsrd, sradi, (1:extsw/5:rldicl)) // P8 BE constant: vspltw, mfvsrwz, (1:extsw/2:rldicl) -// P8 BE variables: sldi, mtvsrd, xxpermdi, vslo, mfvsrd, sradi, (1:extsw) +// P8 BE variables: sldi, mtvsrd, xxpermdi, vslo, mfvsrd, sradi, (1:extsw/2:rldicl)) /* { dg-final { scan-assembler-times {\mvspltw\M} 3 { target lp64 } } } */ /* { dg-final { scan-assembler-times {\mmfvsrwz\M} 3 { target lp64 } } } */ -/* { dg-final { scan-assembler-times {\mrldicl\M} 5 { target { le } } } } */ -/* { dg-final { scan-assembler-times {\mrldicl\M} 2 { target { lp64 && be } } } } */ +/* { dg-final { scan-assembler-times {\mrldicl\M} 7 { target { le } } } } */ +/* { dg-final { scan-assembler-times {\mrldicl\M} 4 { target { lp64 && be } } } } */ /* { dg-final { scan-assembler-times {\msubfic\M} 3 { target { le } } } } */ /* { dg-final { scan-assembler-times {\msldi\M} 3 { target lp64 } } } */ /* { dg-final { scan-assembler-times {\mmtvsrd\M} 3 { target lp64 } } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c index e9dd1131691..e749a2211dd 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c @@ -6,10 +6,10 @@ /* { dg-options "-mdejagnu-cpu=power8 -O2" } */ // six tests total. Targeting P8, both LE and BE. -// p8 (le) variable offset: rldicl, subfic, sldi, mtvsrd, xxpermdi, vslo, mfvsrd, srdi, *extsh -// p8 (le) const offset: mtvsrd, *extsh/rlwinm -// p8 (be) var offset: sldi, mtvsrd, xxpermdi, vslo, mfvsrd, srdi, *extsh -// p8 (be) const offset: vsplth, mfvsrd, *extsh/rlwinm +// p8 (le) variable offset: rldicl, subfic, sldi, mtvsrd, xxpermdi, vslo, mfvsrd, srdi, (1:extsh/2:rlwinm) +// p8 (le) const offset: mtvsrd, (1:extsh/2:rlwinm) +// p8 (be) var offset: sldi, mtvsrd, xxpermdi, vslo, mfvsrd, srdi, (1:extsh:2:rlwinm) +// p8 (be) const offset: vsplth, mfvsrd, (1:extsh/2:rlwinm) // * - each of the above will have an extsh if the argument is signed. // * - bool and unsigned tests also have an rlwinm. @@ -24,7 +24,7 @@ /* { dg-final { scan-assembler-times "mfvsrd" 6 { target lp64 } } } */ /* { dg-final { scan-assembler-times "srdi" 3 { target lp64 } } } */ /* { dg-final { scan-assembler-times "extsh" 2 { target lp64 } } } */ -/* { dg-final { scan-assembler-times "rlwinm" 2 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "rlwinm" 4 { target lp64 } } } */ /* -m32 codegen tests. */ /* { dg-final { scan-assembler-times {\mli\M} 6 { target ilp32 } } } */