From: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date: Fri, 13 Mar 2015 10:48:44 +0000 (+0000)
Subject: [ARM] PR target/64600 Fix another ICE with -mtune=xscale: properly sign-extend mask... 
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=34f1d42665ab2b83863893ec90fe9e8b00a204f2;p=gcc.git

[ARM] PR target/64600 Fix another ICE with -mtune=xscale: properly sign-extend mask during constant splitting

	PR target/64600
	* config/arm/arm.c (arm_gen_constant, AND case): Use
	ARM_SIGN_EXTEND when constructing AND mask.

	PR target/64600
	* gcc.target/arm/pr64600_1.c: New test.

From-SVN: r221413
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index eb5a2d9fc8d..8a24aecda88 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2015-03-13  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/64600
+	* config/arm/arm.c (arm_gen_constant, AND case): Use
+	ARM_SIGN_EXTEND when constructing AND mask.
+
 2015-03-13  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 
 	* graph.c (print_graph_cfg): Make function names visible and append
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 48342d0c0ec..8e484a20377 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -4536,19 +4536,20 @@ arm_gen_constant (enum rtx_code code, machine_mode mode, rtx cond,
 
 	  if ((remainder | shift_mask) != 0xffffffff)
 	    {
+	      HOST_WIDE_INT new_val
+	        = ARM_SIGN_EXTEND (remainder | shift_mask);
+
 	      if (generate)
 		{
 		  rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
-		  insns = arm_gen_constant (AND, mode, cond,
-					    remainder | shift_mask,
+		  insns = arm_gen_constant (AND, SImode, cond, new_val,
 					    new_src, source, subtargets, 1);
 		  source = new_src;
 		}
 	      else
 		{
 		  rtx targ = subtargets ? NULL_RTX : target;
-		  insns = arm_gen_constant (AND, mode, cond,
-					    remainder | shift_mask,
+		  insns = arm_gen_constant (AND, mode, cond, new_val,
 					    targ, source, subtargets, 0);
 		}
 	    }
@@ -4571,12 +4572,13 @@ arm_gen_constant (enum rtx_code code, machine_mode mode, rtx cond,
 
 	  if ((remainder | shift_mask) != 0xffffffff)
 	    {
+	      HOST_WIDE_INT new_val
+	        = ARM_SIGN_EXTEND (remainder | shift_mask);
 	      if (generate)
 		{
 		  rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
 
-		  insns = arm_gen_constant (AND, mode, cond,
-					    remainder | shift_mask,
+		  insns = arm_gen_constant (AND, mode, cond, new_val,
 					    new_src, source, subtargets, 1);
 		  source = new_src;
 		}
@@ -4584,8 +4586,7 @@ arm_gen_constant (enum rtx_code code, machine_mode mode, rtx cond,
 		{
 		  rtx targ = subtargets ? NULL_RTX : target;
 
-		  insns = arm_gen_constant (AND, mode, cond,
-					    remainder | shift_mask,
+		  insns = arm_gen_constant (AND, mode, cond, new_val,
 					    targ, source, subtargets, 0);
 		}
 	    }
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 4a776eec092..152d36cf77f 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2015-03-13  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/64600
+	* gcc.target/arm/pr64600_1.c: New test.
+
 2015-03-12  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
 	PR rtl-optimization/65235
diff --git a/gcc/testsuite/gcc.target/arm/pr64600_1.c b/gcc/testsuite/gcc.target/arm/pr64600_1.c
new file mode 100644
index 00000000000..6ba3fa29690
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pr64600_1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mtune=xscale" } */
+
+typedef unsigned int speed_t;
+typedef unsigned int tcflag_t;
+
+struct termios {
+ tcflag_t c_cflag;
+};
+
+speed_t
+cfgetospeed (const struct termios *tp)
+{
+  return tp->c_cflag & 010017;
+}