From: Luke Kenneth Casson Leighton Date: Sun, 19 Jun 2022 19:40:12 +0000 (+0100) Subject: add absadds - signed accumulating add. DRAFT X-Git-Tag: sv_maxu_works-initial~377 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=350d8301b269fc8b98b491692d2b08545f45781b;p=openpower-isa.git add absadds - signed accumulating add. DRAFT https://bugs.libre-soc.org/show_bug.cgi?id=863 --- diff --git a/openpower/isa/av.mdwn b/openpower/isa/av.mdwn index f4aea8e7..fd5424c8 100644 --- a/openpower/isa/av.mdwn +++ b/openpower/isa/av.mdwn @@ -118,3 +118,20 @@ Pseudo-code: Special Registers Altered: CR0 (if Rc=1) + +# DRAFT Absolute Accumulate Signed Difference + +X-Form + +* absadds RT,RA,RB (Rc=0) +* absadds. RT,RA,RB (Rc=1) + +Pseudo-code: + + if (RA) < (RB) then r <- ¬(RA) + (RB) + 1 + else r <- ¬(RB) + (RA) + 1 + RT <- (RT) + r + +Special Registers Altered: + + CR0 (if Rc=1) diff --git a/openpower/isatables/minor_22.csv b/openpower/isatables/minor_22.csv index c432d601..61f8fc98 100644 --- a/openpower/isatables/minor_22.csv +++ b/openpower/isatables/minor_22.csv @@ -10,3 +10,4 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou 1101001110-,ALU,OP_AVGADD,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,avgadd,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg 1011110110-,ALU,OP_ABSDIFF,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,absdu,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg 1111110110-,ALU,OP_ABSADD,RA,RB,RT,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,absaddu,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +0111110110-,ALU,OP_ABSADD,RA,RB,RT,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,absadds,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg diff --git a/src/openpower/test/bitmanip/av_cases.py b/src/openpower/test/bitmanip/av_cases.py index a5da2fe0..6e689e9f 100644 --- a/src/openpower/test/bitmanip/av_cases.py +++ b/src/openpower/test/bitmanip/av_cases.py @@ -330,3 +330,45 @@ class AVTestCase(TestAccumulatorBase): e.intregs[5] = 0x3 self.add_case(Program(lst, bigendian), initial_regs, expected=e) + def case_0_absadds(self): + lst = ["absadds 3, 1, 2", + "absadds 3, 4, 5", + ] + lst = list(SVP64Asm(lst, bigendian)) + + initial_regs = [0] * 32 + initial_regs[1] = 0x2 + initial_regs[2] = 0x1 + initial_regs[4] = 0x9 + initial_regs[5] = 0x3 + e = ExpectedState(pc=8) + e.intregs[1] = 0x2 + e.intregs[2] = 0x1 + e.intregs[3] = 0x7 + e.intregs[4] = 0x9 + e.intregs[5] = 0x3 + self.add_case(Program(lst, bigendian), initial_regs, expected=e) + + def case_2_absadds(self): + """unlike the absaddu weird case, the 0xfff is treated as signed + so (2) < (-1) and the difference is (2--1)=3. next instruction + adds 6 more. answer: 9 + """ + lst = ["absadds 3, 1, 2", + "absadds 3, 4, 5", + ] + lst = list(SVP64Asm(lst, bigendian)) + + initial_regs = [0] * 32 + initial_regs[1] = 0x2 + initial_regs[2] = 0xffffffffffffffff + initial_regs[4] = 0x9 + initial_regs[5] = 0x3 + e = ExpectedState(pc=8) + e.intregs[1] = 0x2 + e.intregs[2] = 0xffffffffffffffff + e.intregs[3] = 9 + e.intregs[4] = 0x9 + e.intregs[5] = 0x3 + self.add_case(Program(lst, bigendian), initial_regs, expected=e) +