From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 7 Mar 2019 17:08:26 +0000 (-0800)
Subject: Add link to SF2 / igloo2 macro library guide
X-Git-Tag: yosys-0.9~257
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=350dfd3745ec2efa92a601d3bab7712fd9bec07c;p=yosys.git

Add link to SF2 / igloo2 macro library guide

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/techlibs/sf2/cells_sim.v b/techlibs/sf2/cells_sim.v
index f3f7695cf..c62748b11 100644
--- a/techlibs/sf2/cells_sim.v
+++ b/techlibs/sf2/cells_sim.v
@@ -1,3 +1,27 @@
+// https://coredocs.s3.amazonaws.com/Libero/12_0_0/Tool/sf2_mlg.pdf
+
+module ADD2 (
+
+	input A, B,
+	output Y
+);
+	assign Y = A & B;
+endmodule
+
+module ADD3 (
+	input A, B, C,
+	output Y
+);
+	assign Y = A & B & C;
+endmodule
+
+module ADD4 (
+	input A, B, C, D,
+	output Y
+);
+	assign Y = A & B & C & D;
+endmodule
+
 module CFG1 (
 	output Y,
 	input A
@@ -36,27 +60,6 @@ module CFG4 (
 	assign Y = INIT >> {D, C, B, A};
 endmodule
 
-module ADD2 (
-	input A, B,
-	output Y
-);
-	assign Y = A & B;
-endmodule
-
-module ADD3 (
-	input A, B, C,
-	output Y
-);
-	assign Y = A & B & C;
-endmodule
-
-module ADD4 (
-	input A, B, C, D,
-	output Y
-);
-	assign Y = A & B & C & D;
-endmodule
-
 module BUFF (
 	input A,
 	output Y