From: Richard Sandiford Date: Thu, 16 Dec 2021 09:32:00 +0000 (+0000) Subject: aarch64: Add support for Armv9.1-A to Armv9.3-A X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3518022233e6b757c57d3deb7723fd91214fe036;p=binutils-gdb.git aarch64: Add support for Armv9.1-A to Armv9.3-A This patch adds AArch64 support for -march=armv9.[123]-a. The behaviour of the new options can be expressed using a combination of existing feature flags, so we don't need to eat into the vanishing number of spare AARCH64_FEATURE_* bits. Hoewver, it was more convenient to separate out the |s of feature flags so that Armv9.1-A could reuse the set for Armv8.6-A, and so on. include/ * opcode/aarch64.h (AARCH64_ARCH_V8_FEATURES): New macro, split out from... (AARCH64_ARCH_V8): ...here. (AARCH64_ARCH_V8_1_FEATURES): New macro, split out from... (AARCH64_ARCH_V8_1): ...here. (AARCH64_ARCH_V8_2_FEATURES): New macro, split out from... (AARCH64_ARCH_V8_2): ...here. (AARCH64_ARCH_V8_3_FEATURES): New macro, split out from... (AARCH64_ARCH_V8_3): ...here. (AARCH64_ARCH_V8_4_FEATURES): New macro, split out from... (AARCH64_ARCH_V8_4): ...here. (AARCH64_ARCH_V8_5_FEATURES): New macro, split out from... (AARCH64_ARCH_V8_5): ...here. (AARCH64_ARCH_V8_6_FEATURES): New macro, split out from... (AARCH64_ARCH_V8_6): ...here. (AARCH64_ARCH_V8_7_FEATURES): New macro, split out from... (AARCH64_ARCH_V8_7): ...here. (AARCH64_ARCH_V8_8_FEATURES): New macro, split out from... (AARCH64_ARCH_V8_8): ...here. (AARCH64_ARCH_V9_FEATURES): New macro, split out from... (AARCH64_ARCH_V9): ...here. (AARCH64_ARCH_V9_1_FEATURES, AARCH64_ARCH_V9_1): New macros. (AARCH64_ARCH_V9_2_FEATURES, AARCH64_ARCH_V9_2): New macros. (AARCH64_ARCH_V9_3_FEATURES, AARCH64_ARCH_V9_3): New macros. gas/ * doc/c-aarch64.texi: Add armv9.1-a, armv9-2-a and armv9.3-a. * config/tc-aarch64.c (aarch64_archs): Likewise. * NEWS: Mention the above. * testsuite/gas/aarch64/armv9_invalid.d, testsuite/gas/aarch64/armv9_invalid.s, testsuite/gas/aarch64/armv9_invalid.l: New test. * testsuite/gas/aarch64/armv9_1.d, testsuite/gas/aarch64/armv9_1.s: Likewise. * testsuite/gas/aarch64/armv9_1_invalid.d, testsuite/gas/aarch64/armv9_1_invalid.s, testsuite/gas/aarch64/armv9_1_invalid.l: Likewise. * testsuite/gas/aarch64/armv9_2.d, testsuite/gas/aarch64/armv9_2.s: Likewise. * testsuite/gas/aarch64/armv9_2_invalid.d, testsuite/gas/aarch64/armv9_2_invalid.s, testsuite/gas/aarch64/armv9_2_invalid.l: Likewise. * testsuite/gas/aarch64/armv9_3.d, testsuite/gas/aarch64/armv9_3.s: Likewise. --- diff --git a/gas/NEWS b/gas/NEWS index 7d9bb6ba4b0..d0dca5bb035 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -28,7 +28,8 @@ x86 assembler have been reduced from 12 bytes to 10 bytes to match the output of .tfloat directive. -* Add support for 'armv8.8-a' and 'armv9-a' for -march in AArch64 GAS. +* Add support for 'armv8.8-a', 'armv9-a', 'armv9.1-a', 'armv9.2-a' and + 'armv9.3-a' for -march in AArch64 GAS. * Add support for 'armv9-a' for -march in Arm GAS. diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 7277f38a4bb..cc7725483aa 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -9872,6 +9872,9 @@ static const struct aarch64_arch_option_table aarch64_archs[] = { {"armv8.8-a", AARCH64_ARCH_V8_8}, {"armv8-r", AARCH64_ARCH_V8_R}, {"armv9-a", AARCH64_ARCH_V9}, + {"armv9.1-a", AARCH64_ARCH_V9_1}, + {"armv9.2-a", AARCH64_ARCH_V9_2}, + {"armv9.3-a", AARCH64_ARCH_V9_3}, {NULL, AARCH64_ARCH_NONE} }; diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi index 29bfd49207f..8f1f8675b18 100644 --- a/gas/doc/c-aarch64.texi +++ b/gas/doc/c-aarch64.texi @@ -111,7 +111,8 @@ instruction which will not execute on the target architecture. The following architecture names are recognized: @code{armv8-a}, @code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a}, @code{armv8.4-a} @code{armv8.5-a}, @code{armv8.6-a}, @code{armv8.7-a}, @code{armv8.8-a}, -@code{armv8-r}, and @code{armv9-a}. +@code{armv8-r}, @code{armv9-a}, @code{armv9.1-a}, @code{armv9.2-a}, +and @code{armv9.3-a}. If both @option{-mcpu} and @option{-march} are specified, the assembler will use the setting for @option{-mcpu}. If neither are diff --git a/gas/testsuite/gas/aarch64/armv9_1.d b/gas/testsuite/gas/aarch64/armv9_1.d new file mode 100644 index 00000000000..1e6954ba3a5 --- /dev/null +++ b/gas/testsuite/gas/aarch64/armv9_1.d @@ -0,0 +1,12 @@ +#objdump: -dr + +.* + + +Disassembly of section \.text: + +0+ <\.text>: +[^:]*: d50330ff sb +[^:]*: 453f1800 rshrnb z0\.h, z0\.s, #1 +[^:]*: 658aa000 bfcvt z0\.h, p0/m, z0\.s +[^:]*: 45029820 smmla z0\.s, z1.b, z2\.b diff --git a/gas/testsuite/gas/aarch64/armv9_1.s b/gas/testsuite/gas/aarch64/armv9_1.s new file mode 100644 index 00000000000..2d3c9ea5fca --- /dev/null +++ b/gas/testsuite/gas/aarch64/armv9_1.s @@ -0,0 +1,5 @@ + .arch armv9.1-a + sb + rshrnb z0.h, z0.s, #1 + bfcvt z0.h, p0/m, z0.s + smmla z0.s, z1.b, z2.b diff --git a/gas/testsuite/gas/aarch64/armv9_1_invalid.d b/gas/testsuite/gas/aarch64/armv9_1_invalid.d new file mode 100644 index 00000000000..9dffedcb5a8 --- /dev/null +++ b/gas/testsuite/gas/aarch64/armv9_1_invalid.d @@ -0,0 +1 @@ +#error_output: armv9_1_invalid.l diff --git a/gas/testsuite/gas/aarch64/armv9_1_invalid.l b/gas/testsuite/gas/aarch64/armv9_1_invalid.l new file mode 100644 index 00000000000..83be9ceaddd --- /dev/null +++ b/gas/testsuite/gas/aarch64/armv9_1_invalid.l @@ -0,0 +1,2 @@ +[^:]*: Assembler messages: +[^:]*:2: Error: selected processor does not support `ld64b x0,\[x8\]' diff --git a/gas/testsuite/gas/aarch64/armv9_1_invalid.s b/gas/testsuite/gas/aarch64/armv9_1_invalid.s new file mode 100644 index 00000000000..d41e04371f7 --- /dev/null +++ b/gas/testsuite/gas/aarch64/armv9_1_invalid.s @@ -0,0 +1,2 @@ + .arch armv9.1-a + ld64b x0, [x8] diff --git a/gas/testsuite/gas/aarch64/armv9_2.d b/gas/testsuite/gas/aarch64/armv9_2.d new file mode 100644 index 00000000000..590a67dc4c8 --- /dev/null +++ b/gas/testsuite/gas/aarch64/armv9_2.d @@ -0,0 +1,13 @@ +#objdump: -dr + +.* + + +Disassembly of section \.text: + +0+ <\.text>: +[^:]*: d50330ff sb +[^:]*: 453f1800 rshrnb z0\.h, z0\.s, #1 +[^:]*: 658aa000 bfcvt z0\.h, p0/m, z0\.s +[^:]*: 45029820 smmla z0\.s, z1.b, z2\.b +[^:]*: f83fd100 ld64b x0, \[x8\] diff --git a/gas/testsuite/gas/aarch64/armv9_2.s b/gas/testsuite/gas/aarch64/armv9_2.s new file mode 100644 index 00000000000..4a6e34bc685 --- /dev/null +++ b/gas/testsuite/gas/aarch64/armv9_2.s @@ -0,0 +1,6 @@ + .arch armv9.2-a + sb + rshrnb z0.h, z0.s, #1 + bfcvt z0.h, p0/m, z0.s + smmla z0.s, z1.b, z2.b + ld64b x0, [x8] diff --git a/gas/testsuite/gas/aarch64/armv9_2_invalid.d b/gas/testsuite/gas/aarch64/armv9_2_invalid.d new file mode 100644 index 00000000000..b8e21e577c2 --- /dev/null +++ b/gas/testsuite/gas/aarch64/armv9_2_invalid.d @@ -0,0 +1 @@ +#error_output: armv9_2_invalid.l diff --git a/gas/testsuite/gas/aarch64/armv9_2_invalid.l b/gas/testsuite/gas/aarch64/armv9_2_invalid.l new file mode 100644 index 00000000000..750c2f09631 --- /dev/null +++ b/gas/testsuite/gas/aarch64/armv9_2_invalid.l @@ -0,0 +1,5 @@ +[^:]*: Assembler messages: +[^:]*:2: Error: selected processor does not support `cpyfp \[x0\]!,\[x1\]!,x30!' +[^:]*:3: Error: selected processor does not support `cpyfm \[x0\]!,\[x1\]!,x30!' +[^:]*:4: Error: selected processor does not support `cpyfe \[x0\]!,\[x1\]!,x30!' +[^:]*:6: Error: selected processor does not support `bc\.eq 1b' diff --git a/gas/testsuite/gas/aarch64/armv9_2_invalid.s b/gas/testsuite/gas/aarch64/armv9_2_invalid.s new file mode 100644 index 00000000000..bac9a8bd55d --- /dev/null +++ b/gas/testsuite/gas/aarch64/armv9_2_invalid.s @@ -0,0 +1,6 @@ + .arch armv9.2-a + cpyfp [x0]!, [x1]!, x30! + cpyfm [x0]!, [x1]!, x30! + cpyfe [x0]!, [x1]!, x30! +1: + bc.eq 1b diff --git a/gas/testsuite/gas/aarch64/armv9_3.d b/gas/testsuite/gas/aarch64/armv9_3.d new file mode 100644 index 00000000000..b94c85e5f26 --- /dev/null +++ b/gas/testsuite/gas/aarch64/armv9_3.d @@ -0,0 +1,17 @@ +#objdump: -dr + +.* + + +Disassembly of section \.text: + +0+ <\.text>: +[^:]*: d50330ff sb +[^:]*: 453f1800 rshrnb z0\.h, z0\.s, #1 +[^:]*: 658aa000 bfcvt z0\.h, p0/m, z0\.s +[^:]*: 45029820 smmla z0\.s, z1.b, z2\.b +[^:]*: f83fd100 ld64b x0, \[x8\] +[^:]*: 190107c0 cpyfp \[x0\]!, \[x1\]!, x30! +[^:]*: 194107c0 cpyfm \[x0\]!, \[x1\]!, x30! +[^:]*: 198107c0 cpyfe \[x0\]!, \[x1\]!, x30! +[^:]*: 54000010 bc\.eq .* diff --git a/gas/testsuite/gas/aarch64/armv9_3.s b/gas/testsuite/gas/aarch64/armv9_3.s new file mode 100644 index 00000000000..e8bcba3d2a5 --- /dev/null +++ b/gas/testsuite/gas/aarch64/armv9_3.s @@ -0,0 +1,11 @@ + .arch armv9.3-a + sb + rshrnb z0.h, z0.s, #1 + bfcvt z0.h, p0/m, z0.s + smmla z0.s, z1.b, z2.b + ld64b x0, [x8] + cpyfp [x0]!, [x1]!, x30! + cpyfm [x0]!, [x1]!, x30! + cpyfe [x0]!, [x1]!, x30! +1: + bc.eq 1b diff --git a/gas/testsuite/gas/aarch64/armv9_invalid.d b/gas/testsuite/gas/aarch64/armv9_invalid.d new file mode 100644 index 00000000000..582b60f0558 --- /dev/null +++ b/gas/testsuite/gas/aarch64/armv9_invalid.d @@ -0,0 +1 @@ +#error_output: armv9_invalid.l diff --git a/gas/testsuite/gas/aarch64/armv9_invalid.l b/gas/testsuite/gas/aarch64/armv9_invalid.l new file mode 100644 index 00000000000..073c018e012 --- /dev/null +++ b/gas/testsuite/gas/aarch64/armv9_invalid.l @@ -0,0 +1,3 @@ +[^:]*: Assembler messages: +[^:]*:2: Error: selected processor does not support `bfcvt z0\.h,p0/m,z0\.s' +[^:]*:3: Error: selected processor does not support `smmla z0\.s,z1.b,z2\.b' diff --git a/gas/testsuite/gas/aarch64/armv9_invalid.s b/gas/testsuite/gas/aarch64/armv9_invalid.s new file mode 100644 index 00000000000..f1380204b14 --- /dev/null +++ b/gas/testsuite/gas/aarch64/armv9_invalid.s @@ -0,0 +1,3 @@ + .arch armv9-a + bfcvt z0.h, p0/m, z0.s + smmla z0.s, z1.b, z2.b diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 4d4f108f39a..7bd011c4530 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -101,60 +101,82 @@ typedef uint32_t aarch64_insn; /* Crypto instructions are the combination of AES and SHA2. */ #define AARCH64_FEATURE_CRYPTO (AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_AES) +#define AARCH64_ARCH_V8_FEATURES (AARCH64_FEATURE_V8_A \ + | AARCH64_FEATURE_FP \ + | AARCH64_FEATURE_RAS \ + | AARCH64_FEATURE_SIMD) +#define AARCH64_ARCH_V8_1_FEATURES (AARCH64_FEATURE_V8_1 \ + | AARCH64_FEATURE_CRC \ + | AARCH64_FEATURE_LSE \ + | AARCH64_FEATURE_PAN \ + | AARCH64_FEATURE_LOR \ + | AARCH64_FEATURE_RDMA) +#define AARCH64_ARCH_V8_2_FEATURES (AARCH64_FEATURE_V8_2) +#define AARCH64_ARCH_V8_3_FEATURES (AARCH64_FEATURE_V8_3 \ + | AARCH64_FEATURE_PAC \ + | AARCH64_FEATURE_RCPC \ + | AARCH64_FEATURE_COMPNUM) +#define AARCH64_ARCH_V8_4_FEATURES (AARCH64_FEATURE_V8_4 \ + | AARCH64_FEATURE_DOTPROD \ + | AARCH64_FEATURE_FLAGM \ + | AARCH64_FEATURE_F16_FML) +#define AARCH64_ARCH_V8_5_FEATURES (AARCH64_FEATURE_V8_5 \ + | AARCH64_FEATURE_FLAGMANIP \ + | AARCH64_FEATURE_FRINTTS \ + | AARCH64_FEATURE_SB \ + | AARCH64_FEATURE_PREDRES \ + | AARCH64_FEATURE_CVADP \ + | AARCH64_FEATURE_BTI \ + | AARCH64_FEATURE_SCXTNUM \ + | AARCH64_FEATURE_ID_PFR2 \ + | AARCH64_FEATURE_SSBS) +#define AARCH64_ARCH_V8_6_FEATURES (AARCH64_FEATURE_V8_6 \ + | AARCH64_FEATURE_BFLOAT16 \ + | AARCH64_FEATURE_I8MM) +#define AARCH64_ARCH_V8_7_FEATURES (AARCH64_FEATURE_V8_7 \ + | AARCH64_FEATURE_LS64) +#define AARCH64_ARCH_V8_8_FEATURES (AARCH64_FEATURE_V8_8 \ + | AARCH64_FEATURE_MOPS \ + | AARCH64_FEATURE_HBC) + +#define AARCH64_ARCH_V9_FEATURES (AARCH64_FEATURE_V9 \ + | AARCH64_FEATURE_SVE \ + | AARCH64_FEATURE_SVE2) +#define AARCH64_ARCH_V9_1_FEATURES (AARCH64_ARCH_V8_6_FEATURES) +#define AARCH64_ARCH_V9_2_FEATURES (AARCH64_ARCH_V8_7_FEATURES) +#define AARCH64_ARCH_V9_3_FEATURES (AARCH64_ARCH_V8_8_FEATURES) + /* Architectures are the sum of the base and extensions. */ #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ - AARCH64_FEATURE_V8_A \ - | AARCH64_FEATURE_FP \ - | AARCH64_FEATURE_RAS \ - | AARCH64_FEATURE_SIMD) + AARCH64_ARCH_V8_FEATURES) #define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_ARCH_V8, \ - AARCH64_FEATURE_CRC \ - | AARCH64_FEATURE_V8_1 \ - | AARCH64_FEATURE_LSE \ - | AARCH64_FEATURE_PAN \ - | AARCH64_FEATURE_LOR \ - | AARCH64_FEATURE_RDMA) + AARCH64_ARCH_V8_1_FEATURES) #define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_ARCH_V8_1, \ - AARCH64_FEATURE_V8_2) + AARCH64_ARCH_V8_2_FEATURES) #define AARCH64_ARCH_V8_3 AARCH64_FEATURE (AARCH64_ARCH_V8_2, \ - AARCH64_FEATURE_V8_3 \ - | AARCH64_FEATURE_PAC \ - | AARCH64_FEATURE_RCPC \ - | AARCH64_FEATURE_COMPNUM) + AARCH64_ARCH_V8_3_FEATURES) #define AARCH64_ARCH_V8_4 AARCH64_FEATURE (AARCH64_ARCH_V8_3, \ - AARCH64_FEATURE_V8_4 \ - | AARCH64_FEATURE_DOTPROD \ - | AARCH64_FEATURE_FLAGM \ - | AARCH64_FEATURE_F16_FML) + AARCH64_ARCH_V8_4_FEATURES) #define AARCH64_ARCH_V8_5 AARCH64_FEATURE (AARCH64_ARCH_V8_4, \ - AARCH64_FEATURE_V8_5 \ - | AARCH64_FEATURE_FLAGMANIP \ - | AARCH64_FEATURE_FRINTTS \ - | AARCH64_FEATURE_SB \ - | AARCH64_FEATURE_PREDRES \ - | AARCH64_FEATURE_CVADP \ - | AARCH64_FEATURE_BTI \ - | AARCH64_FEATURE_SCXTNUM \ - | AARCH64_FEATURE_ID_PFR2 \ - | AARCH64_FEATURE_SSBS) + AARCH64_ARCH_V8_5_FEATURES) #define AARCH64_ARCH_V8_6 AARCH64_FEATURE (AARCH64_ARCH_V8_5, \ - AARCH64_FEATURE_V8_6 \ - | AARCH64_FEATURE_BFLOAT16 \ - | AARCH64_FEATURE_I8MM) + AARCH64_ARCH_V8_6_FEATURES) #define AARCH64_ARCH_V8_7 AARCH64_FEATURE (AARCH64_ARCH_V8_6, \ - AARCH64_FEATURE_V8_7 \ - | AARCH64_FEATURE_LS64) + AARCH64_ARCH_V8_7_FEATURES) #define AARCH64_ARCH_V8_8 AARCH64_FEATURE (AARCH64_ARCH_V8_7, \ - AARCH64_FEATURE_V8_8 \ - | AARCH64_FEATURE_MOPS \ - | AARCH64_FEATURE_HBC) + AARCH64_ARCH_V8_8_FEATURES) #define AARCH64_ARCH_V8_R (AARCH64_FEATURE (AARCH64_ARCH_V8_4, \ AARCH64_FEATURE_V8_R) \ & ~(AARCH64_FEATURE_V8_A | AARCH64_FEATURE_LOR)) + #define AARCH64_ARCH_V9 AARCH64_FEATURE (AARCH64_ARCH_V8_5, \ - AARCH64_FEATURE_SVE \ - | AARCH64_FEATURE_SVE2 \ - | AARCH64_FEATURE_V9) + AARCH64_ARCH_V9_FEATURES) +#define AARCH64_ARCH_V9_1 AARCH64_FEATURE (AARCH64_ARCH_V9, \ + AARCH64_ARCH_V9_1_FEATURES) +#define AARCH64_ARCH_V9_2 AARCH64_FEATURE (AARCH64_ARCH_V9_1, \ + AARCH64_ARCH_V9_2_FEATURES) +#define AARCH64_ARCH_V9_3 AARCH64_FEATURE (AARCH64_ARCH_V9_2, \ + AARCH64_ARCH_V9_3_FEATURES) #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0) #define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */