From: Luke Kenneth Casson Leighton Date: Thu, 13 Aug 2020 21:23:08 +0000 (+0100) Subject: remove use of latchregigister, replace with sync on rd.go_i X-Git-Tag: semi_working_ecp5~365 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=351cfd0734b5c4c034b5eb9719bb156661508319;p=soc.git remove use of latchregigister, replace with sync on rd.go_i --- diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py index 1045de63..5ec52268 100644 --- a/src/soc/experiment/compldst_multi.py +++ b/src/soc/experiment/compldst_multi.py @@ -372,7 +372,10 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable): for i in range(self.n_src): name = "src_r%d" % i src_r = Signal(self.data_wid, name=name, reset_less=True) - latchregister(m, self.src_i[i], src_r, src_l.q[i], name + '_l') + with m.If(self.rd.go_i[i]): + sync += src_r.eq(self.src_i[i]) + with m.If(self.issue_i): + sync += src_r.eq(0) srl.append(src_r) # and one for the output from the ADD (for the EA) @@ -390,8 +393,8 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable): m.d.comb += src2_or_imm.eq(Mux(op_is_imm, oper_r.imm_data.imm, srl[1])) # now do the ALU addr add: one cycle, and say "ready" (next cycle, too) - sync += alu_o.eq(src1_or_z + src2_or_imm) # actual EA - sync += alu_ok.eq(alu_valid) # keep ack in sync with EA + comb += alu_o.eq(src1_or_z + src2_or_imm) # actual EA + m.d.sync += alu_ok.eq(alu_valid) # keep ack in sync with EA # decode bits of operand (latched) comb += op_is_st.eq(oper_r.insn_type == MicrOp.OP_STORE) # ST