From: Marek Olšák Date: Thu, 4 Jul 2019 02:23:18 +0000 (-0400) Subject: radeonsi: set primitive binning tunables for dGPUs X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3521297251c071a43c00c6e3ac92d27369072e05;p=mesa.git radeonsi: set primitive binning tunables for dGPUs Acked-by: Pierre-Eric Pelloux-Prayer Acked-by: Dave Airlie --- diff --git a/src/gallium/drivers/radeonsi/si_state_binning.c b/src/gallium/drivers/radeonsi/si_state_binning.c index 0720e269c85..39f16971a74 100644 --- a/src/gallium/drivers/radeonsi/si_state_binning.c +++ b/src/gallium/drivers/radeonsi/si_state_binning.c @@ -430,13 +430,18 @@ void si_emit_dpbb_state(struct si_context *sctx) } /* Tunable parameters. Also test with DFSM enabled/disabled. */ - unsigned context_states_per_bin; /* allowed range: [0, 5] */ - unsigned persistent_states_per_bin; /* allowed range: [0, 31] */ + unsigned context_states_per_bin; /* allowed range: [1, 6] */ + unsigned persistent_states_per_bin; /* allowed range: [1, 32] */ unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */ /* Tuned for Raven. Vega might need different values. */ - context_states_per_bin = 5; - persistent_states_per_bin = 31; + if (sscreen->info.has_dedicated_vram) { + context_states_per_bin = 1; + persistent_states_per_bin = 1; + } else { + context_states_per_bin = 6; + persistent_states_per_bin = 32; + } fpovs_per_batch = 63; /* Emit registers. */ @@ -455,8 +460,8 @@ void si_emit_dpbb_state(struct si_context *sctx) S_028C44_BIN_SIZE_Y(bin_size.y == 16) | S_028C44_BIN_SIZE_X_EXTEND(bin_size_extend.x) | S_028C44_BIN_SIZE_Y_EXTEND(bin_size_extend.y) | - S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin) | - S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin) | + S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin - 1) | + S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin - 1) | S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim) | S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) | S_028C44_OPTIMAL_BIN_SELECTION(1) |