From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 18 May 2019 09:12:23 +0000 (+0100)
Subject: connect up vectors direct
X-Git-Tag: div_pipeline~2020
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=352850b7bc945de459a02f7fbb39d4f5b30d3602;hp=758d6e0abe032cf05a09eafeeedae740b2102196;p=soc.git

connect up vectors direct
---

diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py
index 765523e4..99111b9c 100644
--- a/src/experiment/score6600.py
+++ b/src/experiment/score6600.py
@@ -378,6 +378,7 @@ def scoreboard_sim(dut, alusim):
 
             op = randint(0, 1)
             op = i % 2
+            op = 0
         instrs.append((src1, src2, dest, op))
 
     if False:
diff --git a/src/scoreboard/fu_reg_matrix.py b/src/scoreboard/fu_reg_matrix.py
index c583c46e..facd9532 100644
--- a/src/scoreboard/fu_reg_matrix.py
+++ b/src/scoreboard/fu_reg_matrix.py
@@ -119,19 +119,10 @@ class FURegDepMatrix(Elaboratable):
         src2_rsel = []
         for rn in range(self.n_reg_col):
             rsv = regrsv[rn]
-            dest_rsel_o = []
-            src1_rsel_o = []
-            src2_rsel_o = []
-            for fu in range(self.n_fu_row):
-                dc = dm[fu]
-                # accumulate cell reg-select outputs dest/src1/src2
-                dest_rsel_o.append(dc.dest_rsel_o[rn])
-                src1_rsel_o.append(dc.src1_rsel_o[rn])
-                src2_rsel_o.append(dc.src2_rsel_o[rn])
             # connect cell reg-select outputs to Reg Vector In
-            m.d.comb += [rsv.dest_rsel_i.eq(Cat(*dest_rsel_o)),
-                         rsv.src1_rsel_i.eq(Cat(*src1_rsel_o)),
-                         rsv.src2_rsel_i.eq(Cat(*src2_rsel_o)),
+            m.d.comb += [rsv.dest_rsel_i.eq(dc.dest_rsel_o),
+                         rsv.src1_rsel_i.eq(dc.src1_rsel_o),
+                         rsv.src2_rsel_i.eq(dc.src2_rsel_o),
                         ]
             # accumulate Reg-Sel Vector outputs
             dest_rsel.append(rsv.dest_rsel_o)
@@ -150,18 +141,10 @@ class FURegDepMatrix(Elaboratable):
         # ---
         for fu in range(self.n_fu_row):
             dc = dm[fu]
-            dest_i = []
-            src1_i = []
-            src2_i = []
-            for rn in range(self.n_reg_col):
-                # accumulate cell inputs dest/src1/src2
-                dest_i.append(dc.dest_i[rn])
-                src1_i.append(dc.src1_i[rn])
-                src2_i.append(dc.src2_i[rn])
             # wire up inputs from module to row cell inputs (Cat is gooood)
-            m.d.comb += [Cat(*dest_i).eq(self.dest_i),
-                         Cat(*src1_i).eq(self.src1_i),
-                         Cat(*src2_i).eq(self.src2_i),
+            m.d.comb += [dc.dest_i.eq(self.dest_i),
+                         dc.src1_i.eq(self.src1_i),
+                         dc.src2_i.eq(self.src2_i),
                         ]
 
         # ---