From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 12 Jul 2022 09:30:21 +0000 (+0100)
Subject: add FRS as destination to PowerDecoder2 DecodeOut
X-Git-Tag: sv_maxu_works-initial~254
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=353efaa5922c08c320e034feabf5517c7d453b3f;p=openpower-isa.git

add FRS as destination to PowerDecoder2 DecodeOut
---

diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py
index 7ac8c4b4..cc2be39e 100644
--- a/src/openpower/decoder/power_decoder2.py
+++ b/src/openpower/decoder/power_decoder2.py
@@ -385,7 +385,7 @@ class DecodeC(Elaboratable):
 class DecodeOut(Elaboratable):
     """DecodeOut from instruction
 
-    decodes output register RA, RT or SPR
+    decodes output register RA, RT, FRS, FRT, or SPR
     """
 
     def __init__(self, dec, op, regreduce_en):
@@ -412,6 +412,9 @@ class DecodeOut(Elaboratable):
 
         # select Register out field
         with m.Switch(self.sel_in):
+            with m.Case(OutSel.FRS):
+                comb += reg.data.eq(self.dec.FRS)
+                comb += reg.ok.eq(1)
             with m.Case(OutSel.FRT):
                 comb += reg.data.eq(self.dec.FRT)
                 comb += reg.ok.eq(1)