From: Michael Nolan Date: Wed, 24 Jun 2020 17:46:20 +0000 (-0400) Subject: Update comments on LoadStoreUnitInterface X-Git-Tag: div_pipeline~284 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3546f1deed2dc0f7c7715c61e6efd0674562e18d;p=soc.git Update comments on LoadStoreUnitInterface --- diff --git a/src/soc/minerva/units/loadstore.py b/src/soc/minerva/units/loadstore.py index 379b2919..925def86 100644 --- a/src/soc/minerva/units/loadstore.py +++ b/src/soc/minerva/units/loadstore.py @@ -15,18 +15,18 @@ class LoadStoreUnitInterface: self.dbus = Record(wishbone_layout) badwid = addr_wid-log2_int(mask_wid) # TODO: is this correct? + # INPUTS self.x_addr = Signal(addr_wid) # The address used for loads/stores self.x_mask = Signal(mask_wid) # Mask of which bytes to write self.x_load = Signal() # set to do a memory load self.x_store = Signal() # set to do a memory store self.x_store_data = Signal(data_wid) # The data to write when storing - self.x_stall = Signal() # input - do nothing until low - self.x_valid = Signal() - self.m_stall = Signal() # input - do nothing until low - self.m_valid = Signal() # when this is high and m_busy is - # low, the data for the memory load - # can be read from m_load_data + self.x_stall = Signal() # do nothing until low + self.x_valid = Signal() # Not entirely sure yet + self.m_stall = Signal() # do nothing until low + self.m_valid = Signal() # Not entirely sure yet + # OUTPUTS self.x_busy = Signal() # set when the memory is busy self.m_busy = Signal() # set when the memory is busy self.m_load_data = Signal(data_wid) # Data returned from a memory read