From: Jakub Jelinek Date: Sun, 22 May 2016 10:27:27 +0000 (+0200) Subject: sse.md (vec_set_lo_v16hi, [...]): Add alternative with v constraint instead of x... X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=355023cef148556c55768da653b191d826cb6853;p=gcc.git sse.md (vec_set_lo_v16hi, [...]): Add alternative with v constraint instead of x and vinserti32x4 insn. * config/i386/sse.md (vec_set_lo_v16hi, vec_set_hi_v16hi, vec_set_lo_v32qi, vec_set_hi_v32qi): Add alternative with v constraint instead of x and vinserti32x4 insn. * gcc.target/i386/avx512vl-vinserti32x4-3.c: New test. From-SVN: r236568 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 80224c92f1a..809d9d72f9d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,9 @@ 2016-05-22 Jakub Jelinek + * config/i386/sse.md (vec_set_lo_v16hi, vec_set_hi_v16hi, + vec_set_lo_v32qi, vec_set_hi_v32qi): Add alternative with + v constraint instead of x and vinserti32x4 insn. + * config/i386/sse.md (i128vldq): New mode iterator. (avx2_vbroadcasti128_, avx_vbroadcastf128_): Add avx512dq and avx512vl alternatives. diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index e971f1f49d6..b13dff82d39 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -17894,47 +17894,51 @@ (set_attr "mode" "")]) (define_insn "vec_set_lo_v16hi" - [(set (match_operand:V16HI 0 "register_operand" "=x") + [(set (match_operand:V16HI 0 "register_operand" "=x,v") (vec_concat:V16HI - (match_operand:V8HI 2 "nonimmediate_operand" "xm") + (match_operand:V8HI 2 "nonimmediate_operand" "xm,vm") (vec_select:V8HI - (match_operand:V16HI 1 "register_operand" "x") + (match_operand:V16HI 1 "register_operand" "x,v") (parallel [(const_int 8) (const_int 9) (const_int 10) (const_int 11) (const_int 12) (const_int 13) (const_int 14) (const_int 15)]))))] "TARGET_AVX" - "vinsert%~128\t{$0x0, %2, %1, %0|%0, %1, %2, 0x0}" + "@ + vinsert%~128\t{$0x0, %2, %1, %0|%0, %1, %2, 0x0} + vinserti32x4\t{$0x0, %2, %1, %0|%0, %1, %2, 0x0}" [(set_attr "type" "sselog") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") - (set_attr "prefix" "vex") + (set_attr "prefix" "vex,evex") (set_attr "mode" "OI")]) (define_insn "vec_set_hi_v16hi" - [(set (match_operand:V16HI 0 "register_operand" "=x") + [(set (match_operand:V16HI 0 "register_operand" "=x,v") (vec_concat:V16HI (vec_select:V8HI - (match_operand:V16HI 1 "register_operand" "x") + (match_operand:V16HI 1 "register_operand" "x,v") (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3) (const_int 4) (const_int 5) (const_int 6) (const_int 7)])) - (match_operand:V8HI 2 "nonimmediate_operand" "xm")))] + (match_operand:V8HI 2 "nonimmediate_operand" "xm,vm")))] "TARGET_AVX" - "vinsert%~128\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}" + "@ + vinsert%~128\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1} + vinserti32x4\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}" [(set_attr "type" "sselog") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") - (set_attr "prefix" "vex") + (set_attr "prefix" "vex,evex") (set_attr "mode" "OI")]) (define_insn "vec_set_lo_v32qi" - [(set (match_operand:V32QI 0 "register_operand" "=x") + [(set (match_operand:V32QI 0 "register_operand" "=x,v") (vec_concat:V32QI - (match_operand:V16QI 2 "nonimmediate_operand" "xm") + (match_operand:V16QI 2 "nonimmediate_operand" "xm,v") (vec_select:V16QI - (match_operand:V32QI 1 "register_operand" "x") + (match_operand:V32QI 1 "register_operand" "x,v") (parallel [(const_int 16) (const_int 17) (const_int 18) (const_int 19) (const_int 20) (const_int 21) @@ -17944,18 +17948,20 @@ (const_int 28) (const_int 29) (const_int 30) (const_int 31)]))))] "TARGET_AVX" - "vinsert%~128\t{$0x0, %2, %1, %0|%0, %1, %2, 0x0}" + "@ + vinsert%~128\t{$0x0, %2, %1, %0|%0, %1, %2, 0x0} + vinserti32x4\t{$0x0, %2, %1, %0|%0, %1, %2, 0x0}" [(set_attr "type" "sselog") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") - (set_attr "prefix" "vex") + (set_attr "prefix" "vex,evex") (set_attr "mode" "OI")]) (define_insn "vec_set_hi_v32qi" - [(set (match_operand:V32QI 0 "register_operand" "=x") + [(set (match_operand:V32QI 0 "register_operand" "=x,v") (vec_concat:V32QI (vec_select:V16QI - (match_operand:V32QI 1 "register_operand" "x") + (match_operand:V32QI 1 "register_operand" "x,v") (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3) (const_int 4) (const_int 5) @@ -17964,13 +17970,15 @@ (const_int 10) (const_int 11) (const_int 12) (const_int 13) (const_int 14) (const_int 15)])) - (match_operand:V16QI 2 "nonimmediate_operand" "xm")))] + (match_operand:V16QI 2 "nonimmediate_operand" "xm,vm")))] "TARGET_AVX" - "vinsert%~128\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}" + "@ + vinsert%~128\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1} + vinserti32x4\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}" [(set_attr "type" "sselog") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") - (set_attr "prefix" "vex") + (set_attr "prefix" "vex,evex") (set_attr "mode" "OI")]) (define_insn "_maskload" diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 84d1f805a21..2805dc8580f 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,7 @@ 2016-05-22 Jakub Jelinek + * gcc.target/i386/avx512vl-vinserti32x4-3.c: New test. + * gcc.target/i386/avx512dq-vbroadcast-2.c: New test. * gcc.target/i386/avx512vl-vbroadcast-2.c: New test. diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vinserti32x4-3.c b/gcc/testsuite/gcc.target/i386/avx512vl-vinserti32x4-3.c new file mode 100644 index 00000000000..45b0122e925 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vinserti32x4-3.c @@ -0,0 +1,49 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mavx512vl -masm=att" } */ + +typedef char V1 __attribute__((vector_size (32))); +typedef short V2 __attribute__((vector_size (32))); + +void +f1 (V1 x, char y) +{ + register V1 a __asm ("xmm16"); + a = x; + asm volatile ("" : "+v" (a)); + a[7] = y; + asm volatile ("" : "+v" (a)); +} + +void +f2 (V1 x, char y) +{ + register V1 a __asm ("xmm16"); + a = x; + asm volatile ("" : "+v" (a)); + a[28] = y; + asm volatile ("" : "+v" (a)); +} + +void +f3 (V2 x, short y) +{ + register V2 a __asm ("xmm16"); + a = x; + asm volatile ("" : "+v" (a)); + a[3] = y; + asm volatile ("" : "+v" (a)); +} + +void +f4 (V2 x, short y) +{ + register V2 a __asm ("xmm16"); + a = x; + asm volatile ("" : "+v" (a)); + a[14] = y; + asm volatile ("" : "+v" (a)); +} + +/* { dg-final { scan-assembler-times "vinserti32x4\[^\n\r]*0x0\[^\n\r]*%ymm16" 2 } } */ +/* { dg-final { scan-assembler-times "vinserti32x4\[^\n\r]*0x1\[^\n\r]*%ymm16" 2 } } */ +/* { dg-final { scan-assembler-times "vextracti32x4\[^\n\r]*0x1\[^\n\r]*%\[yz]mm16" 2 } } */