From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 11 Dec 2021 23:49:48 +0000 (+0000)
Subject: fix bug in unit test, forgot that wb_get mem dict is 64-bit wide data
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3594a61181079c35bb40d66dc515fee2ed07f17b;p=soc.git

fix bug in unit test, forgot that wb_get mem dict is 64-bit wide data
it cannot cope with addresses non-aligned to 64-bit boundary
---

diff --git a/src/soc/config/test/test_fetch.py b/src/soc/config/test/test_fetch.py
index 5c4097a5..39437b3c 100644
--- a/src/soc/config/test/test_fetch.py
+++ b/src/soc/config/test/test_fetch.py
@@ -13,13 +13,14 @@ import sys
 sys.setrecursionlimit(10**6)
 
 
-def read_from_addr(dut, addr):
+def read_from_addr(dut, addr, stall=True):
     yield dut.a_pc_i.eq(addr)
     yield dut.a_i_valid.eq(1)
     yield dut.f_i_valid.eq(1)
-    yield dut.a_stall_i.eq(1)
-    yield
-    yield dut.a_stall_i.eq(0)
+    if stall:
+        yield dut.a_stall_i.eq(1)
+        yield
+        yield dut.a_stall_i.eq(0)
     yield
     yield Settle()
     while (yield dut.f_busy_o):
diff --git a/src/soc/experiment/test/test_loadstore1.py b/src/soc/experiment/test/test_loadstore1.py
index c1c562b1..f0438d20 100644
--- a/src/soc/experiment/test/test_loadstore1.py
+++ b/src/soc/experiment/test/test_loadstore1.py
@@ -130,25 +130,25 @@ def _test_loadstore1_ifetch_iface(dut, mem):
     i_m_in = icache.m_in
 
     yield from debug(dut, "real mem instruction")
-    # set address to 0x8, update mem[0x8] to 01234
+    # set address to 0x8, update mem[0x8] to 01234 | 0x5678<<32
+    # (have to do 64-bit writes into the dictionary-memory-emulated-thing)
     addr = 8
-    expected_insn = 0x1234
-    mem[addr] = expected_insn
-    # set address to 0xc, update mem[0xc] to 5678
     addr2 = 12
     expected_insn2 = 0x5678
-    mem[addr2] = expected_insn2
+    expected_insn = 0x1234
+    mem[addr] = expected_insn | expected_insn2<<32
 
     yield i_in.priv_mode.eq(1)
-    insn = yield from read_from_addr(icache, addr)
+    insn = yield from read_from_addr(icache, addr, stall=False)
 
     nia   = yield i_out.nia  # NO, must use FetchUnitInterface
     print ("fetched %x from addr %x" % (insn, nia))
     assert insn == expected_insn
 
     print("=== test loadstore instruction (2nd, real) ===")
+    yield from debug(dut, "real mem 2nd (addr 0xc)")
 
-    insn2 = yield from read_from_addr(icache, addr2)
+    insn2 = yield from read_from_addr(icache, addr2, stall=False)
 
     nia   = yield i_out.nia  # NO, must use FetchUnitInterface
     print ("fetched %x from addr2 %x" % (insn2, nia))