From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 8 Mar 2020 17:33:38 +0000 (+0000)
Subject: add combined instruction and register decoder
X-Git-Tag: div_pipeline~1756
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3598480c1be055c608b1eb5285a36c7dc6285481;p=soc.git

add combined instruction and register decoder
---

diff --git a/src/decoder/power_enums.py b/src/decoder/power_enums.py
index 4800bdf2..dcf5cad2 100644
--- a/src/decoder/power_enums.py
+++ b/src/decoder/power_enums.py
@@ -29,6 +29,8 @@ default_values = {'unit': "NONE", 'internal op': "OP_ILLEGAL",
                    'rc' : 'NONE', 'cry in' : 'ZERO', 'form': 'NONE'}
 
 def get_signal_name(name):
+    if name[0].isdigit():
+        name = "is_" + name
     return name.lower().replace(' ', '_')