From: Tim Ansell <me@mith.ro>
Date: Thu, 4 Jul 2019 00:23:36 +0000 (-0700)
Subject: Merge pull request #210 from DurandA/master
X-Git-Tag: 24jan2021_ls180~1130
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=359b8fe4bbda113289a334dcf296eb8856215f2d;p=litex.git

Merge pull request #210 from DurandA/master

Add verilog submodule from CPU cores to manifest
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359b8fe4bbda113289a334dcf296eb8856215f2d