From: lkcl <lkcl@web>
Date: Wed, 27 Jan 2021 22:58:02 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~289
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=35b669b4daabd4bac426323397a3aa740ca4e36d;p=libreriscv.git

---

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index 21feef766..d6529dd9d 100644
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -99,7 +99,7 @@ SV's SVSTATE context is effectively a Sub-PC.  On exceptions the PC is saved int
 
 ## VL for-loop
 
-main SV for-loop, as a FSM, updating `SVSTATE.srcstep`, using it as the index in the for-loop from 0 to VL-1
+main SV for-loop, as a FSM, updating `SVSTATE.srcstep`, using it as the index in the for-loop from 0 to VL-1.  Register numbers are incremented by one if marked as vector.
 
 * ISACaller: TODO
 * power-gem5: TODO