From: Kenneth Graunke Date: Tue, 22 Apr 2014 02:47:07 +0000 (-0700) Subject: i965/skl: Update Viewport Z Clip Test Enable bits for Skylake. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=35bbe177ecea3fdd06d97d0c13beadb75049ac72;p=mesa.git i965/skl: Update Viewport Z Clip Test Enable bits for Skylake. Skylake has separate controls for enabling the Z Clip Test for the near and far planes. For now, maintain the legacy behavior by setting both. Signed-off-by: Kenneth Graunke Reviewed-by: Kristian Høgsberg Reviewed-by: Anuj Phogat --- diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 950f97a1368..3725452bc98 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -1914,6 +1914,7 @@ enum brw_message_target { #define _3DSTATE_RASTER 0x7850 /* GEN8+ */ /* DW1 */ +# define GEN9_RASTER_VIEWPORT_Z_FAR_CLIP_TEST_ENABLE (1 << 26) # define GEN8_RASTER_FRONT_WINDING_CCW (1 << 21) # define GEN8_RASTER_CULL_BOTH (0 << 16) # define GEN8_RASTER_CULL_NONE (1 << 16) @@ -1924,6 +1925,7 @@ enum brw_message_target { # define GEN8_RASTER_LINE_AA_ENABLE (1 << 2) # define GEN8_RASTER_SCISSOR_ENABLE (1 << 1) # define GEN8_RASTER_VIEWPORT_Z_CLIP_TEST_ENABLE (1 << 0) +# define GEN9_RASTER_VIEWPORT_Z_NEAR_CLIP_TEST_ENABLE (1 << 0) /* Gen8 BLEND_STATE */ /* DW0 */ diff --git a/src/mesa/drivers/dri/i965/gen8_sf_state.c b/src/mesa/drivers/dri/i965/gen8_sf_state.c index 0a15d9c2984..1d7b93261ac 100644 --- a/src/mesa/drivers/dri/i965/gen8_sf_state.c +++ b/src/mesa/drivers/dri/i965/gen8_sf_state.c @@ -291,8 +291,14 @@ upload_raster(struct brw_context *brw) dw1 |= GEN8_RASTER_SCISSOR_ENABLE; /* _NEW_TRANSFORM */ - if (!ctx->Transform.DepthClamp) - dw1 |= GEN8_RASTER_VIEWPORT_Z_CLIP_TEST_ENABLE; + if (!ctx->Transform.DepthClamp) { + if (brw->gen >= 9) { + dw1 |= GEN9_RASTER_VIEWPORT_Z_NEAR_CLIP_TEST_ENABLE | + GEN9_RASTER_VIEWPORT_Z_FAR_CLIP_TEST_ENABLE; + } else { + dw1 |= GEN8_RASTER_VIEWPORT_Z_CLIP_TEST_ENABLE; + } + } BEGIN_BATCH(5); OUT_BATCH(_3DSTATE_RASTER << 16 | (5 - 2));