From: lkcl <lkcl@web>
Date: Sat, 12 Mar 2022 23:08:13 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~3087
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=35bbedd4f0a77290c27730201112c2222636ee6a;p=libreriscv.git

---

diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn
index 2a9efc724..e9d62fd00 100644
--- a/openpower/sv/bitmanip.mdwn
+++ b/openpower/sv/bitmanip.mdwn
@@ -174,7 +174,7 @@ bits 21..22 may be used to specify a mode, such as treating the whole integer ze
 ## ternlog
 
 a 5 operand variant which becomes more along the lines of an FPGA,
-this is very expensive: 4 in and 1 out
+this is very expensive: 4 in and 1 out  and is not recommended.
 
 | 0.5|6.10|11.15|16.20|21.25| 26...30  |31|
 | -- | -- | --- | --- | --- | -------- |--|