From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 21 Oct 2018 07:53:58 +0000 (+0100)
Subject: move sv_insn_t constructor to c file
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=35be4cb90276bc0b16d066f93f72d3ed0ccd69bf;p=riscv-isa-sim.git

move sv_insn_t constructor to c file
---

diff --git a/riscv/sv.cc b/riscv/sv.cc
index f1a302d..9d6a637 100644
--- a/riscv/sv.cc
+++ b/riscv/sv.cc
@@ -2,6 +2,22 @@
 #include "sv_decode.h"
 #include "processor.h"
 
+sv_insn_t::sv_insn_t(processor_t *pr, bool _sv_enabled,
+            insn_bits_t bits, unsigned int f,
+            uint64_t &p_rd, uint64_t &p_rs1, uint64_t &p_rs2, uint64_t &p_rs3,
+            uint64_t &p_sp, uint64_t *p_im,
+            int *o_rd, int *o_rs1, int *o_rs2, int *o_rs3, int *o_sp,
+            int *o_imm) :
+            insn_t(bits), p(pr), sv_enabled(_sv_enabled), vloop_continue(false),
+            at_least_one_reg_vectorised(false), fimap(f),
+            offs_rd(o_rd), offs_rs1(o_rs1), offs_rs2(o_rs2), offs_rs3(o_rs3),
+            offs_sp(o_sp),
+            offs_imm(o_imm),
+            prd(p_rd), prs1(p_rs1), prs2(p_rs2), prs3(p_rs3), psp(p_sp),
+            save_branch_addr(0)
+{
+}
+
 sv_pred_entry* sv_insn_t::get_predentry(uint64_t reg, bool intreg)
 {
   // okaay so first determine which map to use.  intreg is passed
diff --git a/riscv/sv_decode.h b/riscv/sv_decode.h
index c1e3854..9dfb890 100644
--- a/riscv/sv_decode.h
+++ b/riscv/sv_decode.h
@@ -29,14 +29,7 @@ public:
             uint64_t &p_rd, uint64_t &p_rs1, uint64_t &p_rs2, uint64_t &p_rs3,
             uint64_t &p_sp, uint64_t *p_im,
             int *o_rd, int *o_rs1, int *o_rs2, int *o_rs3, int *o_sp,
-            int *o_imm) :
-            insn_t(bits), p(pr), sv_enabled(_sv_enabled), vloop_continue(false),
-            at_least_one_reg_vectorised(false), fimap(f),
-            offs_rd(o_rd), offs_rs1(o_rs1), offs_rs2(o_rs2), offs_rs3(o_rs3),
-            offs_sp(o_sp),
-            offs_imm(o_imm),
-            prd(p_rd), prs1(p_rs1), prs2(p_rs2), prs3(p_rs3), psp(p_sp),
-            save_branch_addr(0) {}
+            int *o_imm);
 
   uint8_t reg_elwidth(reg_t reg, bool intreg);
   sv_reg_t rvc_addi4spn_imm() { return sv_reg_t(insn_t::rvc_addi4spn_imm()); }