From: Raptor Engineering Development Team <support@raptorengineering.com>
Date: Thu, 31 Mar 2022 07:39:31 +0000 (-0500)
Subject: Fix Tercel QSPI master connections
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=35cad0c484d8dd3747c73ec2a783e13a3b557da7;p=ls2.git

Fix Tercel QSPI master connections

Tested to work on Raptor Versa 85 custom board
in both word and byte mode.
---

diff --git a/src/ls2.py b/src/ls2.py
index f3ad84d..55a7b65 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -44,6 +44,11 @@ from gram.phy.fakephy import FakePHY, SDRAM_VERBOSE_STD, SDRAM_VERBOSE_DBG
 from gram.modules import MT41K256M16, MT41K64M16
 from gram.frontend.wishbone import gramWishbone
 
+# SPI
+from nmigen.build import Resource
+from nmigen.build import Subsignal
+from nmigen.build import Pins
+
 # Board (and simulation) platforms
 from nmigen_boards.versa_ecp5 import VersaECP5Platform
 from nmigen_boards.versa_ecp5 import VersaECP5Platform85 # custom board
@@ -412,6 +417,7 @@ class DDR3SoC(SoC, Elaboratable):
             # The main SPI Flash (SPI 1) should be set to at
             # least 28 bits (256MB) to allow the use of large 4BA devices.
             self.spi0 = Tercel(data_width=32, spi_region_addr_width=24,
+                               adr_offset=spi0_addr,
                                features={'stall'},
                                clk_freq=clk_freq,
                                pins=spi_0_pins,
@@ -669,24 +675,19 @@ def build_platform(fpga, firmware):
 
     # Get SPI resource pins
     spi_0_pins = None
-    if platform is not None and fpga in ['rcs_arctic_tern_bmc_card',
-                                         'isim',
-                                         'arty_a7',
-                                         'versa_ecp5_85',
-                                         'versa_ecp5']:
-        # XXX naming-conventions for nmigen_boards/resources/interface.py
-        # SPIResource are "spi" not "spi_0", and for SPIFlashResources
-        # the name convention is "spi_flash_1x" (or 2x or 4x)
-        if toolchain == 'Trellis':
-            # The ECP5 series FPGAs handle the SPI clock directly on
-            # the FPGA configuration Flash device
-            spi_0_pins = platform.request("spi_flash_4x", 0,
-                                        dir={"dq":"io", "cs":"o"},
-                                        xdr={"dq": 1, "cs": 1})
-        else:
-            spi_0_pins = platform.request("spi_flash_4x", 0,
-                                        dir={"dq":"io", "cs":"o", "clk":"o"},
-                                        xdr={"dq": 1, "cs": 1, "clk": 0})
+    if platform is not None and \
+       fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim']:
+        # Override here to get FlashResource out of the way and enable Tercel
+        # direct access to the SPI flash
+        spi_0_ios = [ Resource("spi_0", 0,
+                                        Subsignal("dq",   Pins("W2 V2 Y2 W1", dir="io")),
+                                        Subsignal("cs_n", Pins("R2", dir="o")),
+                                        Attrs(PULLMODE="NONE", DRIVE="4",
+                                        IO_TYPE="LVCMOS33")) ]
+        platform.add_resources(spi_0_ios)
+        spi_0_pins = platform.request("spi_0", 0, dir={"dq":"io", "cs_n":"o"},
+                                                  xdr={"dq":1, "cs_n":0})
+
     print ("spiflash pins", spi_0_pins)
 
     # Get Ethernet RMII resource pins