From: lkcl <lkcl@web>
Date: Thu, 3 Oct 2019 08:11:43 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~3921
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=35e1ad6818b2e0077c1ce455fe4d4d62a731277a;p=libreriscv.git

---

diff --git a/simple_v_extension/specification/bitmanip.mdwn b/simple_v_extension/specification/bitmanip.mdwn
index 0a572b7be..a78a64d47 100644
--- a/simple_v_extension/specification/bitmanip.mdwn
+++ b/simple_v_extension/specification/bitmanip.mdwn
@@ -220,17 +220,25 @@ Pseudo-code:
 
     def sof(rd, rs1, rs2):
         rd = 0
-        # search mode starts on
-        search_mode = True
+        setting_mode = rs2 == x0 or (regs[rs2] & 1)
         while i < XLEN:
             bit = 1<<i
-            if search_mode:
+            if setting_mode:
                 if regs[rs1] & bit: # found a bit in rs1:
+                    # set bit, exit setting mode immediately
                     regs[rd] |= bit
-                    search_mode = False
+                    setting_mode = False
+                    # Now skip any more 1s
+                    i += 1
+                    while i < XLEN:
+                        bit = 1<<i
+                        # stop at 1st zero
+                        if regs[rs1] & bit == 0:
+                            break
+                        i += 1
             else if rs2 != x0:
                 # only reenable when predicate in use, and bit valid
                 if (regs[rs2] & bit):
-                    search_mode = True # back into "search" mode
+                    setting_mode = True # back into "setting" mode
             i += 1