From: Pat Haugen <pthaugen@us.ibm.com>
Date: Wed, 21 Dec 2016 19:15:32 +0000 (+0000)
Subject: re PR rtl-optimization/11488 (Pre-regalloc scheduling severely worsens performance)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=35f4cbd4489519983a4f64da846be8352f611879;p=gcc.git

re PR rtl-optimization/11488 (Pre-regalloc scheduling severely worsens performance)

	PR rtl-optimization/11488
	* common/config/rs6000/rs6000-common.c
	(rs6000_option_optimization_table): Enable -fsched-pressure.
	* config/rs6000/rs6000.c (TARGET_COMPUTE_PRESSURE_CLASSES): Define
	target hook.
	(rs6000_option_override_internal): Set default -fsched-pressure algorithm.
	(rs6000_compute_pressure_classes): Implement target hook.

From-SVN: r243866
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 0a7f34a8cd4..1454cce9c5d 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2016-12-21  Pat Haugen  <pthaugen@us.ibm.com>
+
+	PR rtl-optimization/11488
+	* common/config/rs6000/rs6000-common.c
+	(rs6000_option_optimization_table): Enable -fsched-pressure.
+	* config/rs6000/rs6000.c (TARGET_COMPUTE_PRESSURE_CLASSES): Define
+	target hook.
+	(rs6000_option_override_internal): Set default -fsched-pressure algorithm.
+	(rs6000_compute_pressure_classes): Implement target hook.
+
 2016-12-21  Bill Seurer  <seurer@linux.vnet.ibm.com>
 
 	PR sanitizer/65479
diff --git a/gcc/common/config/rs6000/rs6000-common.c b/gcc/common/config/rs6000/rs6000-common.c
index af297ba67a6..88e5ff62eb8 100644
--- a/gcc/common/config/rs6000/rs6000-common.c
+++ b/gcc/common/config/rs6000/rs6000-common.c
@@ -32,6 +32,8 @@
 static const struct default_options rs6000_option_optimization_table[] =
   {
     { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
+    /* Enable -fsched-pressure for first pass instruction scheduling.  */
+    { OPT_LEVELS_1_PLUS, OPT_fsched_pressure, NULL, 1 },
     { OPT_LEVELS_NONE, 0, NULL, 0 }
   };
 
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index a870d60ae7c..77bb5486392 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -1807,6 +1807,9 @@ static const struct attribute_spec rs6000_attribute_table[] =
 #undef TARGET_LRA_P
 #define TARGET_LRA_P rs6000_lra_p
 
+#undef TARGET_COMPUTE_PRESSURE_CLASSES
+#define TARGET_COMPUTE_PRESSURE_CLASSES rs6000_compute_pressure_classes
+
 #undef TARGET_CAN_ELIMINATE
 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
 
@@ -5107,6 +5110,12 @@ rs6000_option_override_internal (bool global_init_p)
 			     global_options.x_param_values,
 			     global_options_set.x_param_values);
 
+      /* Use the 'model' -fsched-pressure algorithm by default.  */
+      maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM,
+			     SCHED_PRESSURE_MODEL,
+			     global_options.x_param_values,
+			     global_options_set.x_param_values);
+
       /* If using typedef char *va_list, signal that
 	 __builtin_va_start (&ap, 0) can be optimized to
 	 ap = __builtin_next_arg (0).  */
@@ -37961,6 +37970,32 @@ rs6000_lra_p (void)
   return TARGET_LRA;
 }
 
+/* Compute register pressure classes.  We implement the target hook to avoid
+   IRA picking something like NON_SPECIAL_REGS as a pressure class, which can
+   lead to incorrect estimates of number of available registers and therefor
+   increased register pressure/spill.   */
+static int
+rs6000_compute_pressure_classes (enum reg_class *pressure_classes)
+{
+  int n;
+
+  n = 0;
+  pressure_classes[n++] = GENERAL_REGS;
+  if (TARGET_VSX)
+    pressure_classes[n++] = VSX_REGS;
+  else
+    {
+      if (TARGET_ALTIVEC)
+	pressure_classes[n++] = ALTIVEC_REGS;
+      if (TARGET_HARD_FLOAT && TARGET_FPRS)
+	pressure_classes[n++] = FLOAT_REGS;
+    }
+  pressure_classes[n++] = CR_REGS;
+  pressure_classes[n++] = SPECIAL_REGS;
+
+  return n;
+}
+
 /* Given FROM and TO register numbers, say whether this elimination is allowed.
    Frame pointer elimination is automatically handled.