From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 16 Apr 2018 01:03:09 +0000 (+0100)
Subject: add comparison section
X-Git-Tag: convert-csv-opcode-to-binary~5664
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=360da7854aed6b48fe6dfc11eedb16117a95fded;p=libreriscv.git

add comparison section
---

diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn
index c9308e28f..6d7eba88f 100644
--- a/simple_v_extension.mdwn
+++ b/simple_v_extension.mdwn
@@ -1117,7 +1117,10 @@ RVV (as it stands, Draft 0.4 Section 17, RISC-V ISA V2.3-Draft)
   be able to do so if "indirect" features of Simple-V are partially adopted).
 * plus-and-slight-minus: extended variants may address up to 256
   vectorised registers (requires 48/64-bit opcodes to do it).
-
+* minus-and-partial-plus: separate engine plus complexity increases
+  implementation time and die area, meaning that adoption is likely only
+  to be in high-performance specialist supercomputing (where it will
+  be absolutely superb).
 
 # Impementing V on top of Simple-V